Graphene and III-V channel metal-oxide-semiconductor field-effect devices for post-Si CMOS applications
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To meet the demands for continuous transistor scaling and performance improvements required by the ITRS, there has been a tremendous amount of effort related to alternative high mobility channel materials as potential Si replacements for MOSFET fabrication. Two particularly attractive material systems include III-V substrates and graphene. Thus far, the high trap density which characterizes high-κ dielectrics and the III-V/high-κ dielectric interface remains an obstacle to III-V substrate integration. In a first aspect of this work, charge traps within the gate stack of III-V MOSFETs, as well as at the III-V/dielectric interface, were examined to better understand their impact on III-V device performance. In particular, a pulsed I-V measurement technique was used to assess the impact of fast and slow transient charging effects on various III-V transistors with ALD-deposited Al2O3 gate dielectric. The charge pumping technique was also utilized to determine the density of interface traps, including their energy distribution and position profile, providing further understanding into the nature of traps in the III-V/high-κ system. Graphene has also attracted considerable interest owing to its high intrinsic mobility, large current densities, thermodynamic and mechanical stability. Yet, a primary challenge to the integration of graphene substrates is the lack of high quality, large-area graphene. Thus, in another aspect of this work, large-area graphene was synthesized by CVD of acetylene on Co thin films, and the influence of Co film thickness on graphene synthesis was studied. Resulting graphene films were characterized using Raman spectroscopy and back-gated GFETs were fabricated. Taking advantage of graphene’s intrinsic ambipolar electron-hole symmetry, GFET frequency doublers were fabricated on low-capacitance, single-crystal quartz substrates. GFETs frequency doublers were found to operate beyond their transit frequency (fT), and in the limit of vanishing device non-idealities, their maximum conversion gain was determined to approach a near lossless value. To further understand and improve GFET RF performance, the impact of parasitic resistances was experimentally examined. RF measurements as a function of temperature and modulated access resistance highlight the strong influence of RC on scaled devices, while the impact of RA becomes more evident for devices with large access regions.