A comparative study of adders
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This report compares the area, delay, and gate count complexity of 8, 16, 32, and 64 bit versions of several types of adders. For the purpose of the study, ripple carry adders, carry look-ahead adders, carry select adders, carry skip adders and Kogge Stone adders were used. To fulfill the study, the adders were implemented in structural Verilog using only 2-input NAND and NOR gates and inverters. The adders were synthesized using Design Vision (by Synopsys). Auto Place and Route was performed using Cadence Encounter to get the layout of the adders and then Parasitic Extraction was performed to get the actual routing delay. Primetime was used to calculate the post synthesis and post place and route delays. Post-PNR netlist was used to compare the area, and delay of the different adders.
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