Automatic generation of instruction sequences for software-based self-test of processors and systems-on-a-chip
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At-speed functional tests are an important part of the manufacturing test flow of processors. With delay defects becoming more common due to the properties of the newer process technologies, at-speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache to test the processor for defects. Generally, only random instructions are used in nativemode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. We propose an automatic technique that alleviates the need for such manual effort. Our technique has a hierarchical approach. We use traditional automatic test pattern generation (ATPG) algorithms for generating tests at the local level (module or combinational blocks). These tests are mapped to instructions at the global level using a verification engine. We also have feedback between these two levels for more efficient testing. We demonstrate the technique on a publicly available processor. We then enhance the technique to test an entire system-on-a-chip (SOC). A typical SOC has an embedded processor. We use this embedded processor to test the other blocks in the SOC. In general, most of these blocks are designed by the design reuse methodology. Therefore, these blocks may be available only as black-boxes. Our technique is well suited to test such blocks. We use existing test vectors for the core and present a technique that generates instruction sequences that when executed by the processor generates the given vectors at the boundaries of the blocks. We designed an SOC using an ARM core and a publicly available encryption core and experimented on it to demonstrate the effectiveness of our technique.