High speed 128-point Fast Fourier Transform circuit design for OFDM
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The Fast Fourier Transform (FFT) Algorithm is an efficient way to calculate the Discrete Fourier Transform, which is widely used in digital signal processing. Due to the increasing demand for Orthogonal Frequency Division Multiplexing (OFDM) wireless communication systems, it becomes even more important today. For the current Ultra Wide Band standard, the data sampling rate is 528 MHz. This thesis proposes a high-speed hardware FFT which targets next generation wireless communication systems with a 3.6 GHz sampling rate. This thesis is organized as follows. Chapter 1 introduces the motivation and the flow of the proposed design. Chapter 2 presents background knowledge of the Discrete Fourier Transform and the Fast Fourier Transform based on the Cooley- Tukey decomposition. It includes the basic theory and as well as the method to simplify the algorithm. Chapters 3 and 4 describe the design of the high speed arithmetic components for the FFT module. In Chapter 3, several high performance adders are implemented and compared. Chapter 4 discusses high speed multipliers. Implementation of a Dadda multiplier is also introduced. The conversion of the FFT from algorithm to hardware is explained in Chapter 5, which addresses several issues of concern as well as the tradeoffs between different approaches. Chapter 5 also presents the structure of the FFT and simulation results. Chapter 6 gives a summary of the work and points out the direction of future work.