A comparative study of adders
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This report compares the area, delay, complexity (in terms of gate count) and power of 16, 32 and 64 bit versions of different types of serial and parallel adders. Ripple carry adder, Carry look-ahead adder, carry select adder and parallel prefix adders like Brent-Kung, Kogge-Stone, Han-Carlson and Ladner-Fischer were studied. For the parallel adders schematics were designed in Cadence Virtuoso Schematic Editor using 2 input NAND, NOR and INVERTER gate as the standard cells in 45nm technology. The other adders were implemented using structural Verilog and synthesized using Design Vision (by Synopsys). Auto Place and Route was performed using Cadence Encounter to get the layout of the adders and then Parasitic Extraction was performed to get the actual routing delay. Post-PNR netlist was used to compare the area, delay and power of the various adders. Area-Delay product was used as a figure of merit to compare the adders.
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