Area, delay and power comparison of adder topologies
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An adder is an indispensable component for a processing system and is ever-present on an integrated circuit. With scaling and the increasing levels of integration seen in the contemporary integrated circuits, power consumption has become an important factor in deciding the performance of any adder circuit in addition to the speed. Area has always been another factor which is taken into account based on the application. This work provides a comprehensive analysis of the standard cell based CMOS implementations of six adder topologies of different word sizes in 45nm technology. The analysis is done on leakage power, dynamic power, speed and area. The switching activities of the circuits were captured using dynamic gate level simulation to perform the time based peak power analysis. Static timing analysis was performed to estimate the delay of the critical path for each circuit. The complexity of the circuit is decided based on the number of gates used in the implementation and the area utilized by the standard cells in the circuit. The analysis and results presented in this report will be helpful in choosing a specific adder configuration for an integrated circuit based on the constraints related to its application.