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dc.contributor.advisorKwong, Dim-Leeen
dc.creatorWen, Huang-Chunen
dc.date.accessioned2008-08-28T23:52:29Zen
dc.date.available2008-08-28T23:52:29Zen
dc.date.issued2006en
dc.identifier.urihttp://hdl.handle.net/2152/3511en
dc.description.abstractAs the CMOS integrated circuits are reduced to the 100-nanometer regime, the conventional SiO2-based gate dielectrics are facing serious scaling challenges. High-k materials are expected to replace SiO2 as the gate insulator. However, metal gates are coherently needed to replace poly-Si due to the increase in threshold voltage for high-k stacks with poly-Si gates and the poly depletion effect. The challenge in metal gate research is to obtain metals with effective work function (EWF) values of ~5.0-5.2eV for p-MOS and 4.1-4.3eV for n-MOS. Although EWF should be determined predominately by the vacuum WF of the materials, it is observed that the EWF is different on high-k than on SiO2. One proposed mechanism to limit the EWF tuning on high-k dielectrics, and a possible inherent roadblock to the identification of band-edge metals, is the Fermilevel pinning effect Metal gate EWF has been systematically studied with the goal of identifying band-edge metal gate electrode candidates. The terraced oxide technique has been developed as the metric for accurate EWF extraction. A comparison of the literature Fermi-level pinning models with our experimental data shows that an intrinsic limitation (pinning at the high-k charge neutrality level) may not exist and the source of most EWF deviation on high-k is due to extrinsic contributions, such as interfacial reactions. Both the bulk metal characteristics and the interface properties between the metal and dielectric have been found to control overall EWF. Charges can be induced in the gate stack during device processing and shift the flatband voltage (Vfb). Engineering of the EWF by an interface dipole has been identified as a plausible approach for EWF tuning. Aluminum-containing electrode stacks and lanthanide electrode stacks are proposed as potential p-type and n-type metal candidates. The potential impact of candidate metal systems on device performance and reliability was studied, as well as other materials that may reveal implications for the influence of the electrode on the gate stack. Comparison of the deposition techniques, shows that even physical vapor deposited (PVD) metal electrodes can exhibit high performance. Metals with high O reactivity will reduce the high-k and consequently degrade electron mobility. No long term reliability concerns were observed for the candidate metals.
dc.format.mediumelectronicen
dc.language.isoengen
dc.rightsCopyright © is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subject.lcshMetal oxide semiconductors, Complementaryen
dc.subject.lcshDielectricsen
dc.subject.lcshGate array circuitsen
dc.subject.lcshSilicon oxideen
dc.subject.lcshMetal oxide semiconductor field-effect transistorsen
dc.titleSystematic evaluation of metal gate electrode effective work function and its influence on device performance in CMOS devicesen
dc.description.departmentElectrical and Computer Engineeringen
dc.identifier.oclc182858110en
dc.type.genreThesisen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophyen


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