Design of particle mitigating wafer chucks for yield enhancement

As the semiconductor industry drives down the minimum feature size on wafers to increase performance and device density, the necessary site flatness of a standard 26 x 33 mm field becomes much more stringent. A significant unresolved cause for non-planarity is particle contamination at the interface of the wafer substrate and the wafer chuck. The result is an out of plane distortion that can affect a significant portion of the wafer resulting in device yield loss. This research looks at two methods for mitigating the effects of particle contamination. The first method investigates using an in-situ cleaning approach in a wafer chuck to eliminate particles. This concept is called a Particle Eliminating Pin (PEP) chuck. The second method proposes enhancements to a wafer chuck design based on compliant mechanisms resulting in a chuck that is tolerant of particle contamination, referred to here as the enhanced compliant pin chuck (E-CPC). The PEP chuck was explored relative to well-established methods for removing back-side particles and demonstrated it could eliminate an additional 18.5% of particles that could not be removed via the well-established methods. Additional potential effectiveness of a PEP chuck is also discussed based on future improvements. A scaled prototype of the proposed new design of the E-CPC was fabricated and tested as well. The prototype validated most of the proposed improvements but failed to maintain the mechanism’s rotational requirement. With the understanding gained from this design and experimental research a future design of the E-CPC has been proposed in the future research section such that this new design can achieve all the proposed goals while still maintaining the required mechanism rotation.