Logic and clock network optimization in nanometer VLSI circuits
MetadataShow full item record
Logic optimization and clock network optimization for power, performance and area trade-off have been imperative problems for the very large scale integrated (VLSI) circuit designers. With further technology scaling, complex designs and aggressive time-to-market targets, scalable algorithms are very much anticipated than ever before. The logic optimizations can be at pre-synthesis stage, post-synthesis stage or even cross-layer. The success of the logic optimization is determined by how much it can benefit in metrics such as power and performance after physical placement and routing. Meanwhile, building a process variation tolerant and On-Chip-Variation (OCV) aware clock network to meet the performance/power target in modern designs has become an extremely difficult job, which calls for clock tree resynthesis, i.e., restructuring of an existing clock network, to achieve better power/performance. This dissertation first focuses on a pre-synthesis logic optimization problem, high performance adder synthesis. The optimization of the prefix network, capturing the carry-computation of any adder, has been shown to be effective even after logic synthesis, placement and routing over existing adder solutions, including even hand-made custom adders designed in industrial designs. Second a post-synthesis optimization problem, a new paradigm of discrete gate sizing under multiple operating conditions, is proposed to consider both system and logic level information. Besides it helps in design space exploration by providing feedback to the system level. Our paradigm is flexible to integrate various reliability and physical design issues. Finally, a clock network optimization problem, clock tree resynthesis, is proposed to achieve multi-corner, multi-mode timing closure and dynamic power minimization on an already synthesized and routed clock tree. The clock tree resynthesis algorithms have been integrated into an industrial placement and routing tool, and validated on large-scale industrial designs.