Graphene and MoS2 devices for wafer-scale integrated silicon nanotechnology

Abstract

The largest applications of layered two-dimensional (2D) materials such as graphene and transition metal dichalcogenides (TMDs) will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology. The two grand challenges to realize this goal are wafer-scalable device development which preserves the high performance of mechanically-exfoliated 2D films, and integration of 2D materials onto Si CMOS via scalable bonding transfer.

To address the first challenge, we investigate the scalable growth of polycrystalline graphene and MoS2 through chemical vapor deposition (CVD) and their integration with Si VLSI technology. Material characterization techniques (STM, XTEM and XRD) are used to investigate the quality of the grown graphene film. The uniformity of the grown film is probed through large-area Raman mapping on 150 and 300 mm Si substrates and reveals > 95% monolayer uniformity with negligible defects. The electrical properties of the grown film on 100 mm substrate are investigated by transferring it to a target Si substrate. About 26,000 graphene field-effect transistors (GFETs) were realized by conventional Si-CMOS compatible fabrication method. The field-effect mobility, sheet and contact resistance are investigated on a statistically large number of devices chosen randomly. Intrinsic graphene features such as soft current saturation, three-region output characteristics at high electric field and frequency doubler and amplifiers are observed on the wafer-scale. Our growth and transport results on scalable CVD graphene have enabled 300 mm synthesis instrumentation that is now commercially available.

Using similar growth and development mechanisms, we investigated the large-area growth of monolayer MoS2 on Si platform and probed the electrical properties of the film by using a platform of back-gated field-effect transistors (FET).

To address the second grand challenge, we developed a novel method for mechanical delamination of graphene onto an arbitrary target substrate that potentially can be scaled up to wafer-scale. Large area and high quality graphene synthesized on Cu film, using the above-mentioned process, is transferred to a Si substrate using a novel direct mechanical delamination process based on fracture mechanics. The electrical characterization of the transferred film indicates the good quality of the mechanically delaminated graphene and holds great promise for the future integration of 2D materials with Si-CMOS.