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dc.contributor.advisorGharpurey, Ranjit
dc.creatorForbes, Travis Michael, 1986-en
dc.date.accessioned2015-03-02T19:05:32Zen
dc.date.issued2013-12en
dc.date.submittedDecember 2013en
dc.identifier.urihttp://hdl.handle.net/2152/28712en
dc.descriptiontexten
dc.description.abstractThe functionality provided by mobile devices such as cellular phones and tablets continues to increase over the years, with integration of an ever larger number of wireless standards within a given device. In several of these designs, each standard supported by a device requires its own IC receiver to be mounted on the device’s PCB. In multistandard and multimode radios, it is desirable to integrate all receivers onto the same IC as the digital processors for the standards, in order to reduce device cost and size. Ideally all the receivers should also share a single signal chain. Since each standard has its own requirements for linearity and noise figure, and each standard operates at a different RF carrier frequency, implementing such a receiver is very challenging. Such a receiver could be theoretically implemented using a broadband mixing receiver or by direct sampling by a high-speed analog-to-digital converter (ADC). Broadband mixing requires the use of a harmonic rejection mixer (HRM) or tunable band pass filter to remove harmonic mixing effects, which in the past have suffered from a large primary clock tuning range and high power consumption. However, direct sampling of the RF input requires a high-speed ADC with large dynamic range which is typically limited by clock timing skew, clock jitter, or harmonic folding. In this dissertation, techniques for programmable broadband radio receivers are proposed. A local oscillator (LO) synthesis method within HRMs is proposed which reduces the required primary clock tuning range in broadband receivers. The LO synthesis method is implemented in 130-nm CMOS. A clocking technique is introduced within the two-stage HRM, which helps in achieving state-of-the-art harmonic rejection performance without calibration or harmonic filtering. An analog frequency synthesis based broadband channelizer is proposed using the LO synthesis method which is capable of channelizing a broadband input using a single mixing stage and primary clock frequency. A frequency-folded ADC architecture is proposed which enables high-speed sampling with high dynamic range. A receiver based on the frequency-folded ADC architecture is implemented in 65-nm CMOS and achieves a sample rate of 2-GS/s, a mean 49-dB SNDR, and 8.5-dB NF.en
dc.format.mimetypeapplication/pdfen
dc.subjectSoftware-defined radioen
dc.subjectBroadband mixeren
dc.subjectCMOSen
dc.subjectDirect-conversionen
dc.subjectHarmonic mixingen
dc.subjectHarmonic rejectionen
dc.subjectLO synthesisen
dc.subjectMismatchen
dc.subjectMixeren
dc.subjectNoise cancellationen
dc.subjectPassive mixeren
dc.subjectProgrammable frequencyen
dc.subjectReceiveren
dc.subjectRF mixeren
dc.subjectBroadbanden
dc.subjectFrequency-foldeden
dc.subjectADCen
dc.subjectChannelized receiveren
dc.subjectImage rejectionen
dc.subjectClock jitteren
dc.subjectSource-follower filteren
dc.subjectDirect samplingen
dc.titleCircuit techniques for programmable broadband radio receiversen
dc.typeThesisen
dc.date.updated2015-03-02T19:05:33Zen
dc.description.departmentElectrical and Computer Engineeringen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophyen


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