Parametric testing, characterization and reliability of integrated circuits
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This work deals with the problem of parametric failures in Integrated Circuits (ICs), focussing specifically on timing, which is one of the most important parameters in modern ICs. Two approaches to tackling timing violations are explored, the first being efficient timing characterization, involving delay test and debug, to screen out defective parts, and the second, timing oriented adaptive design for variability related failures. Timing violations are a major source of defective silicon for ICs designed in Deep Sub-micron (DSM) technologies. This is because the performance requirements of such ICs are very high, leading to reduced slack margins, and also because defects and variations in process parameters significantly impact their behavior. However, smaller feature sizes and higher levels of integration, which are characteristic of DSM ICs, have severely limited their controllability and observability, hence hindering efficient timing characterization. In vii this work, techniques to enhance controllability and observability for timing characterization of ICs, using novel Design for Test and Design for Debug techniques are presented. In addition to defects, variations in process parameters also impact the behavior of DSM ICs, and can cause a large number of defect free parts to fail the test process and be discarded, leading to reduction in manufacturing yield. An approach for combatting variations is the use of adaptive or variation aware design. In this work, adaptive design techniques with a focus on timing, i.e., performance-optimized adaptive design, are explored. These techniques ensure that adaptation does not cause a chip to violate timing specifications, and also enable a chip to reconfigure itself to reduce or eliminate variability related timing violations, hence enabling parametric reliability in ICs.