High-permittivity dielectrics and high mobility semiconductors for future scaled technology: Hf-based High-K gate dielectrics and interface engineering for HfO₂/Ge CMOS device
For more than 40 years, MOS device technologies have been improving at a dramatic rate. These technologies need to meet the requirements of performance (speed), low static (off-state) power, and a wide range of power supply and output voltage to fuel market expansion. The greater performance at lower cost requires an increased circuit density and shrunken dimensions. The rapid shrinking of the transistor feature size has forced gate dielectric thickness decrease, which pushes SiO2 down to the physical limit. Currently, high permittivity material, such as HfO2, has been extensively studied due to its suitable dielectric constant (22-25), wide band gap (~5.6eV) and thermal stability in contact to Si. However, high k dielectrics have also faced lots of integration challenges, such as charge trapping and mobility degradation. Moreover, as the EOT of HfO2 gate dielectric is scaled down to the sub-nm regime, the gate leakage current increases quickly and is not acceptable for any practical application. In this research, the Hf-based higher k HfTaTiO and HfTiAlO gate dielectrics are demonstrated with both dielectric constants more than 25. The stability and scalability are investigated. Both dielectrics can be scaled down to below 1nm with acceptable leakage current. Improved mobility and reliability are studied. In addition, further power-performance gain is likely to be achieved by incorporating the benefit of the ultra-high channel mobility offered by Ge semiconductor. Changing the substrate from silicon to germanium brings new challenges in the formation of high k gate stacks. The poor quality of Ge native dielectric for gate insulator and field isolation has been one of the problems. The novel pre-gate clean has been developed for effective native oxide removal. Two interface passivation processes, NH3 annealing and Si interlayer, have been demonstrated. They reduce the leakage current density, C-V hysteresis and interface state density. Ge diffusion model is proposed and it suggests the necessity of a proper surface preparation prior to the dielectric film deposition. All the new materials and process development in this research present some potential solutions to enable high performance and low power CMOS for future technology.