Reliability study on the via of dual damascene Cu interconnects
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The function of an interconnect system is to distribute signals and power to various circuits in a chip. The goal of the interconnect development is to achieve high speed transmission in the chips despite continued down-scaling of feature size. The interconnect signal delay, known as resistance-capacitance (RC) delay, can be a bottleneck for the signal transmission speed. The National Technology Roadmap for Semiconductors (NTRS) 1994 first described the need of new conductor and dielectric materials (known as Cu/low-k) which were different from the conventional Al(Cu) and SiO2 in an attempt to mitigate the RC delay and meet the technology requirements. Since then, interconnect materials and structures have been rapidly changing, creating significant and new reliability challenges. Chips with Cu/SiO2 interconnects were introduced in 1998 [1, 2, 3] to reduce the interconnect resistance. To lower dielectric constant, fluoro-silicate glass (FSG, k = 3.7) was implemented for the 180 nm node [1, 2, 3], and organo-silicate glass (OSG, k = 2.7 ~ 3.0) was used for the 90 nm node . However, the reliability issues related to these materials and dual damascene structures proved to be more challenging than anticipated. The integration of porous low-k materials has been even more difficult. The reduction of feature sizes, implementation of new materials and their integration into dual damascene structures all pose a challenge in developing interconnects with good reliability.