New methodology for low power and less test time in VLSI testing

Recently, the rapid growth of integrated circuit (IC) has brought up many challenges in IC testing industry. The most challenging problems are the overhead of power dissipation, of test data volume, and of test time. These three challenges are expected to get worse as IC gets more complex and the system-on chip (SOC) gets deeper and more embedded. This dissertation addresses these three challenges thoroughly and then offers the solutions to alleviate their seriousness. These solutions are so well shaped that their performance results turn out to be quite impressive and significant. It is proved by the simulation with the various benchmark circuits, ISCAS’85 and ISCAS’89. Furthermore, this dissertation discusses about the future work, some of which are closely related to the present work. The future work deals with new application of the present work, its possible further improvements, and its new investigation in terms of power dissipation, test data volume, and test time.