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dc.contributor.advisorHo, P. S.
dc.creatorWu, Zhuojieen
dc.date.accessioned2014-07-11T20:10:36Zen
dc.date.issued2013-05en
dc.date.submittedMay 2013en
dc.identifier.urihttp://hdl.handle.net/2152/25145en
dc.descriptiontexten
dc.description.abstractThe continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes.en
dc.format.mimetypeapplication/pdfen
dc.subjectSemiconductoren
dc.subjectInterconnectsen
dc.subjectElectromigrationen
dc.subjectElectron wind forceen
dc.subjectScalingen
dc.subjectResistance traceen
dc.subjectVoiden
dc.subjectScatteringen
dc.subjectReactive ion etchingen
dc.subjectElectron beam lithographyen
dc.subjectAnisotropic wet etchingen
dc.subjectStressen
dc.subjectModelingen
dc.titleStudy of initial void formation and electron wind force for scaling effects on electromigration in Cu interconnectsen
dc.typeThesisen
dc.date.updated2014-07-11T20:10:37Zen
dc.description.departmentPhysicsen
thesis.degree.departmentPhysicsen
thesis.degree.disciplinePhysicsen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophyen


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