Electronic and spintronic transport in germanium nanostructures
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The digital information processing system has benefited tremendously from the invention and development of complementary metal-oxide-semiconductor (CMOS) integrated circuits. The relentless scaling of the physical dimensions of transistors has been consistently delivering improved overall circuit density and performance every technology generation. However, the continuation of this trend is in question for silicon-based transistors when quantum mechanical tunneling becomes more relevant; further scaling in feature sizes can lead to increased leakage current and power dissipation. Numerous research efforts have been implemented to address these scaling challenges, either by aiming to increase the performance at the transistor level or to introduce new functionalities at the circuit level. In the first approach, novel materials and device structures are explored to improve the performance of CMOS transistors, including the use of high-mobility materials (e.g. III-V compounds and germanium) as the channel, and multi-gate structures. On the other hand, the overall circuit capability could be increased if other state variables are exploited in the electronic devices, such as the electron spin degree of freedom (e.g. spintronics). Here we explore the potential of germanium nanowires in both CMOS and beyond-CMOS applications, studying the electronic and spintronic transport in this material system. Germanium is an attractive replacement to silicon as the channel material in CMOS technology, thanks to its lighter effective electron and hole mass. The nanowire structures, directly synthesized using chemical vapor deposition, provide a natural platform for multi-gate structures in which the electrostatic control of the gate is enhanced. We present the realization and scaling properties of germanium-silicon-germanium core-shell nanowire n-type, [omega]-gate field-effect transistors (FETs). By studying the channel length dependence of NW FET characteristics, we conclude that the intrinsic channel resistance is the main limiting factor of the drive current of Ge NW n-FETs. Utilizing the electron spins in semiconductor devices can in principle enhance overall circuit performance and functionalities. Electrical injection of spin-polarized electrons into a semiconductor, large spin diffusion length, and an integration friendly platform are desirable ingredients for spin based-devices. Here we demonstrate lateral spin injection and detection in Ge NWs, by using ferromagnetic metal contacts and tunnel barriers for contact resistance engineering. We map out the contact resistance window for which spin transport is observed, manifestly showing the conductivity matching required for spin injection.