The effects of silicon, nitrogen and oxygen incorporation and oxygen-scavenging technique on performances of hafnium-based gate dielectric MOSFETs
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The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV-1 cm -2), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. According to ITRS (International Technology Roadmap for Semiconductor) roadmap, the EOT (equivalent oxide thickness) in MOSFETs for next generation technology node must be below ~15Å for both high performance logic application like microprocessor and low power application such as mobile electronics. However, as the dramatic scaling-down is continuously needed, ultra thin silicon dioxide cannot be useful any more as a gate dielectric because the use of ultra thin SiO2 gate dielectrics gives rise to a number of problems, including high gate leakage current, reduced drive current, reliability degradation, B (boron) penetration, and the need to grow ultra thin and uniform layer. Especially, the physical limit and reliability problem of ulta thin SiO2 result from significantly increased direct tunneling current in such a thin region. Therefore, the need for new gate dielectric materials is emerging to reduce leakage current while maintaining a low EOT. Many materials with a dielectric constant higher than that of SiO2, known as high k dielectrics, have been being investigated in order to identify a SiO2 replacement. So far, HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The phase transformation due to crystallization of dielectric can provide the formation of gain boundary that will act as high oxygen or dopants diffusivity path, making EOT scaling problematic and causing device failure with high leakage current. Nitrogen incorporation into high k materials has been investigated to achieve further scaling and improve thermal and electrical stability because nitrogen is known to suppress oxygen diffusion, and reduce low k interfacial layer growth at the Si interface. However, nitrogen incorporation alone can result in several potential problems. Since nitrogen is likely to bind to Si, most of the nitrogen incorporated tends to pile up at the Si interface. This leads to an increased interface trapped charge density, increased hysteresis and lower channel mobility due to coulombic scattering. Also, the amount of nitrogen incorporated can be limited due to nitrogen out-diffusion during anneals. A potential solution to these problems is incorporating Si to modulate the nitrogen profile since Si traps nitrogen and suppresses nitrogen out-diffusion. In the first part of this study, the effects of nitrogen and silicon on Hf-based MOSFET performances and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen profile has been modulated by inserting Si layer into HfOxNy. Nitrogen incorporation enhanced Vth shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer. Although nitrogen incorporation reduces interfacial reaction and results in aggressive thinning such as EOT below10Å, which is required for beyond 65nm design rule, it also induces disadvantages such as higher hysteresis, higher charge trapping and degraded channel carrier mobility due to trap charges caused by nitrogen itself. Therefore, for aggressive scaling with good interface quality, novel process without using nitrogen, which can suppress low k interfacial regrowth, should be delivered. Some transition metals like Hf, Zr and Ti have very high oxygen solubility as well as negative free energy of oxide formation. These properties can be used to decompose SiO2 like low k interfacial oxide upon appropriate annealing (i.e., oxygen scavenging effect) and produce further EOT scaling. As for second part of this study, for highly scaled gate dielectric application, a novel oxygen scavenging approach has been proposed and investigated. A novel process has been developed to achieve ultra-thin gate dielectrics (EOT<0.7nm) without involving nitrogen incorporation by engineering interface oxide thickness. Interfacial oxide formation was suppressed by the “oxygen-scavenging effect” using Hf metal on underlying HfO2 device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO2. Using this fabrication approach, EOT of ~0.9nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55~0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect. Excellent charge trapping and MOSFET characteristics have been demonstrated.