Advanced fabrication processes for sub-50nm CMOS
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Scaling CMOS technology into sub-50 nm has presented a significant new challenge for the semiconductor community. In these devices, silicon oxide gate dielectric and poly-silicon gate electrode need to be replaced with high-k and metal, respectively, due to the limitation of scaling gate dielectrics and high gate leakage current. One of the major challenges in this new high-k/metal CMOS implementation is the advanced process integration of dual metal gate CMOS to realize nanoscale CMOS operation. Therefore, in this thesis, deposition-etch-deposition based dual metal gate CMOS integration has been deeply explored. Highly selective wet process development, its integration issues, effect on high-k dielectric surface, impacts on CMOS performance has been investigated. Primary research results have been used to integrate complete dual metal gate CMOS and the significant device data have been presented. In addition, thermal annealing effects have been probed to examine physical property change in a representative high-k/metal film stack. Finally, a comparative study and feasibility of a simplistic method has been discussed and future research direction has been pointed out.