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dc.contributor.advisorSun, Nan
dc.creatorJin, Xiankunen
dc.date.accessioned2014-04-21T14:32:16Zen
dc.date.issued2013-12en
dc.date.submittedDecember 2013en
dc.identifier.urihttp://hdl.handle.net/2152/24051en
dc.descriptiontexten
dc.description.abstractThe static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip signal generator has made it prohibitive. The stimulus error identification and removal (SEIR) method has greatly reduced the linearity requirement. However, it requires a highly stable voltage offset, which remains a daunting task. This work exploits the inherit capacitive sample-and-hold circuit used in various ADC architectures to inject offset with very good constancy. A 16-bit successive approximate register (SAR) ADC with the proposed BIST scheme is modeled and simulated in Matlab to prove its validity. The results show that the estimation error on the maximum INL is less than 0.07 LSB. This BIST solution is then naturally extended to the calibration of an ADC. It is shown missing codes of such ADC can be effectively estimated and calibrated out.en
dc.format.mimetypeapplication/pdfen
dc.subjectADC BISTen
dc.subjectSEIRen
dc.subjectDigital calibrationen
dc.subjectSAR ADCen
dc.subjectOffset injectionen
dc.titleA SEIR-based ADC built-in-self-test and its application in ADC self-calibrationen
dc.typeThesisen
dc.date.updated2014-04-21T14:32:16Zen
dc.description.departmentElectrical and Computer Engineeringen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen


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