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dc.contributor.advisorSun, Nan
dc.creatorFontaine, Robert Alexanderen
dc.date.accessioned2014-04-15T20:02:13Zen
dc.date.issued2013-12en
dc.date.submittedDecember 2013en
dc.identifier.urihttp://hdl.handle.net/2152/24011en
dc.descriptiontexten
dc.description.abstractThe Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed.en
dc.format.mimetypeapplication/pdfen
dc.subjectSARen
dc.subjectSuccessive Approximation Registeren
dc.subjectADCen
dc.subjectFlip-flop bypassen
dc.titleInvestigation of 10-bit SAR ADC using flip-flip bypass circuiten
dc.typeThesisen
dc.date.updated2014-04-15T20:02:13Zen
dc.description.departmentElectrical and Computer Engineeringen
thesis.degree.departmentElectrical and Computer Engineeringen
thesis.degree.disciplineElectrical and Computer Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelMastersen
thesis.degree.nameMaster of Science in Engineeringen


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