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    Software optimization for power consumption in DSP embedded systems

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    Temple_report_20122.pdf (1.090Mb)
    Date
    2012-05
    Author
    Temple, Andrew Richard
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    Abstract
    This paper is intended to be a resource for programmers needing to optimize a DSP’s power consumption strictly through software. The paper will provide a basic introduction into power consumption background, measurement techniques, and then go into the details of power optimization, focusing on three main areas: algorithmic optimization, taking advantage of hardware features (low power modes, clock control, and voltage control), and data flow optimization with a discussion into the functionality and power considerations when using fast SRAM type memories (common for cache) and DDR SDRAM. This work includes examples and results as tested on Freescale’s current state of the art Digital Signal Processors.
    Department
    Electrical and Computer Engineering
    Description
    text
    Subject
    Low power
    Clock gating
    Embedded programming
    Power modes
    URI
    http://hdl.handle.net/2152/22607
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