Characterization and reliability of HFO₂ and hfsion gate dielectrics with tin metal gate
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Since the invention of the integrated circuit in 1958, the semiconductor industry has progressed at a fiery pace, through aggressive shrinking of the transistor channel length and associated device dimensions. The problems associated with such aggressive scaling are many-fold and have been dealt with by clever modifications or additions to existing process technology. However, as the 65 nm technology node nears production, the semiconductor industry hits a fundamental physical limitation: The thickness of the gate dielectric, Silicon Dioxide (SiO2) has been reduced to such an extent that the tunneling leakage current through the gate stack is reaching untenable levels. High permittivity dielectrics or high-κ dielectrics are being investigated to replace SiO2 in order to preserve the capacitance while maintaining larger physical thickness to keep the leakage current down. However, the introduction of high-κ materials into the conventional process flow is rendered difficult by various issues. It has been shown that gate stacks with high-κ materials have severely degraded mobility, while possessing large densities of charge traps. Additional concerns include the pinning of Fermi level at the midgap of the silicon bandgap, yielding undesirable threshold voltages, dielectric phase separation in ternary high-κ materials, high interface state density, low crystallization temperature and growth of a low-κ interfacial layer. We present a systematic study of the reliability aspects of hafnium based dielectrics with TiN gate electrode, and propose a robust and reliabile dielectric for introduction into CMOS product flow. Stress induced leakage current or SILC is studied in thick HfO2 dielectrics with TiN gate electrode and it has been observed that significant low voltage SILC-like behavior is exhibited when nMOSFETs and pMOSFETs are stressed under positive biased stress. Such SILC behavior is also shown to be reversible when a negative voltage is applied after the stress, or if the devices are relaxed with a 0V bias. This reversible low-voltage SILC is attributed to electrons being trapped during the stress, which subsequently detrap during the I-V sweeps, leading to the appearance of SILC-like behavior. Mobility degradation in high-κ gate stacks is studied and it is proposed that the mobility degradation is a combination of remote coulomb scattering, due to fixed charges in the dielectric and phonon scattering. Thinning the high-κ dielectric down is offered as a solution to reduce the mobility degradation. Positive bias temperature instability is studied, and it is shown that the threshold voltage instability can be reduced to insignificant levels by reducing the thickness of the dielectric. However, the threshold voltage instability of thick high-κ dielectrics remains problematic and will need to be solved before high-κ gate stacks can be incorporated into low power applications. It is shown that incorporating nitrogen into the dielectric through plasma nitridation or thermal nitridation could be used to reduce charge trapping in thick dielectrics. Negative bias temperature instability is shown to be a combination of electron detrapping from the high-κ layer and interface state creation due to hole injection into the interfacial layer. Although the interface state creation is made slightly worse by thinning the dielectric down, the threshold voltage shift is still less significant in thin dielectrics. While the introduction of high-κ dielectrics can now be considered viable, caution needs to applied while integrating metal gates into the product flow, for the problem of fermi-level pinning still remains unsolved. An outline of all the remaining issues with such high-κ / metal gate gate stacks is presented at the end of this report.