System modeling of CMOS power amplifier employing envelope and average power tracking for efficiency enhancement
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In the past decade, there has been great motivation to improve the efficiency of power amplifiers (PAs) in handset transmitter systems in order to address critical issues such as poor battery life and excessive heat. Currently, the focus lies on high data rate applications such as wideband code division multiple access (WCDMA) and long term evolution (LTE) standards due to the stringent efficiency and linearity requirements on the PA. This thesis describes a simulation-based study of techniques for enhancing the efficiency of a CMOS power amplifier for WCDMA and LTE applications. The primary goal is to study the concepts of envelope and average power tracking in simulation and to demonstrate the effectiveness of these supply modulation techniques on a CMOS PA design. The P1dB and IMD performance of a Class A/AB CMOS PA has been optimized to operate with high peak-to-average modulation with WCDMA and LTE signals. Behavioral models of envelope and average power tracking are implemented using proposed algorithms, and a system-level analysis is performed. Envelope tracking is seen to offer a peak PAE improvement of 15% for WCDMA, versus a fixed voltage supply, while average power tracking renders a maximum efficiency gain of 9.8%. Better than -33dBc adjacent channel leakage-power ratio (ACLR) at 5MHz offset and EVM below 4% are observed for both supply tracking techniques. For LTE, envelope and average power tracking contribute to a peak PAE enhancement of 15.3% and 7%, respectively. LTE ACLR begins failing the -30dBc specification above 22.5dBm output power during envelope tracking operation in the PA implementation described here.