A study on the nanocrystal floating-gate nonvolatile memory
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This dissertation presents the theoretical analysis and experimental results of the nanocrystal floating-gate nonvolatile memory devices. The problems in scaling down the conventional floating-gate nonvolatile memory device have been investigated, and the motivation of the nanocrystal floating-gate is introduced. Thanks to the electrical and physical isolation between each nanocrystal, nanocrystal structure is basically stronger than the conventional floating-gate to the defects in the dielectrics, resulting in the better device reliability. The dielectrics of the nonvolatile memory device, and the floating-gate surrounded by the dielectics, have been studied with respect to the associated electrical characteristics in order to optimize the device performance. The role of the tunneling dielectric for the better programming / retention trade-off is investigated, and the high-k dielectric is proposed for this reason. It turns out that the larger physical thickness and the lower electron barrier height of the HfO2 high-k barrier than the conventional SiO2 barrier is beneficial to improve the program / retention performance of the memory cell. The motivations of the workfunction engineering of the floating-gate are introduced based on the high-k tunneling barrier, to further improve the nonvolatility of the memory device. Theoretical analysis has been performed to validate the advantages of the workfunction engineering in floating-gate nonvolatile memory device. Nickel metal nanocrystal floating-gate is proposed to improve the data retention characteristic by providing the larger workfunction than the Si floating-gate. Process development has been performed to achieve the optimized size and density of the nickel nanocrystal floating-gate, and the memory transistor with nickel nanocrystal embedded in the high-k dielectrics has been fabricated and evaluated. The memory device with the TiN floating-gate has also been fabricated and characterized. The comparison of the nanocrystal and continuous floating-gate has been discussed as well. Forler-Nordheim tunneling has been used both for the programming and erasing of the high-k nanocrystal memory in this work. The programming instability caused by the Forler-Nordheim programming has been theoretically investigated. It turns out that the charges are no longer able to be stored inside the nanocrystal floating-gate at high programming voltage such that the tunneling mechanisms in both tunneling and control barrier are dominated by Forler Norheim tunneling. The control barrier with the higher barrier height is proposed to overcome the programming instability. Based on the theoretical analysis, the memory transistor with the Si3N4 control barrier and Si nanocrystal / HfO2 tunneling barrier has been fabricated and characterized.