Scalable voltage reference for ultra deep submicron technologies
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A CMOS voltage reference architecture is shown that operates at a power supply that is equal to two threshold voltages. The circuit designed includes no more than two devices stacked between Vdd and Vss , thus allowing for the circuit to scale with device sizing (technology). The circuit is demonstrated in a 0.18µ and 0.09µ process that operates at a power supply voltage of 0.9V and 0.4V, respectfully. The dissertation discusses the motivation behind scaling the MOSFET transistor and the challenges that scaling introduces to analog circuit design in general. The voltage reference is a basic building block for most analog circuits, and therefore must be able to scale with technology. The temperature characteristics of silicon and MOSFET devices are discussed in order to develop analog circuits that demonstrate specific and controlled temperature characteristics. By describing the temperature characteristics of these devices with polynomials, the Method of Least Squares may be used to determine gain coefficients that give an optimum temperature independent voltage reference.