System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications

As high precision data acquisition systems continue to improve their performance and power efficiency to migrate into portable devices, increasing demands are placed on the performance and power efficiency of the analog-to-digital conversion modulator. On the other hand, analog-to-digital modulator performance is largely limited by several major noise sources including thermal noise, flicker noise, quantization noise leakage and internal analog and digital coupling noise. Large power consumption and die area are normally required to suppress the above noise energies, which are the major challenges to achieve power efficiency and cost targets for modern day high precision converter design. The main goal of this work is to study various approaches and then propose and validate the most suitable topology to achieve the desired performance and power efficiency specifications, up to 100 kHz bandwidth with 16-21 bits of resolution. This work will first study various analog-to-digital conversion architectures ranging from Nyquist converters such as flash, pipeline, to the delta sigma architecture. Advantages and limitations of each approach will be compared to develop the criteria for the optimal modulator architecture. Second, this work will study analog sub-circuit blocks such as opamp, comparator and reference voltage generator, to compare the advantages and limitations of various design approaches to develop the criteria for the optimal analog sub circuit design. Third, this work will study noise contributions from various sources such as thermal noise, flicker noise and coupling noise, to explore alternative power and die area efficient approaches to suppress the noise. Finally, a new topology will be proposed to meet all above criteria and adopt the new noise suppression concepts, and will be demonstrated to be the optimal approach. The main difference between this work from previous ones is that current work places emphasis on the integration of the modulator architecture design and analog sub-circuit block research efforts. A high performance stereo analog-to-digital modulator is designed based on the new approach and manufactured in silicon. The chip is measured in the lab and the measurement results reported in the dissertation.