Architecture and implementation of intelligent transceivers for ultra-wideband communications
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The wide bandwidth employed in the UWB system allows for high data-rate communications, while its broadband nature requires it to coexist with other systems. For instance, several communication systems, such as digital TV, wireless LANs, WiMAX, and satellite receivers, utilize spectrum that is in the UWB band. According to Federal Communications Commission (FCC) regulations, the power spectral density (PSD) of UWB devices for communication applications is limited to less than -41.25dBm/MHz in the 3.1-10.6GHz frequency band, to minimize the impact of UWB on other systems. The impact of narrowband signals on UWB systems can also be significant, even though these signals may occupy a small part of the UWB spectrum, due to their much larger power. The performance and capacity of UWB systems can be significantly degraded by these narrowband interferers. In-band interference can be tolerated by increasing the dynamic-range of the receiver such that the interferers are accommodated within the linear range of the receiver. Alternatively, if the interferers can be avoided altogether, the excessive linearity requirements imposed by the interferers can be relaxed. Such an avoidance mechanism requires the ability to detect interferers. This work presents a low-power and low-cost detector for this purpose that can be employed in multi-band approaches to UWB, including pulse-based schemes, and those employing OFDM. The UWB band is divided into narrower sub-bands in these schemes. During transmission, the carrier hops to a new sub-band every symbol. The detector is designed to provide a profile of interference over the entire UWB spectrum, during each symbol period. This information would be available to the main-path UWB receiver to decide a frequency sequence of sub-band hopping, in order to avoid sub-bands occupied by large interferers. This relaxes the dynamic-range requirement, and hence the power dissipation of the main-path receiver, thus compensating for the extra power dissipation of the detector. The detector is based on a cascade of image-reject downconverter stages. An implementation of the architecture is demonstrated in a 0.13[mu]m CMOS process.