Step and flash imprint lithography : materials and applications for the manufacture of advanced integrated circuits
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Step-Flash Imprint Lithography (S-FIL[trademark]) is a low-cost, high-resolution, high-throughput pattern replication process with the potential to become the savior for the future of integrated circuit (IC) manufacturing where continued success ultimately depends on improvements in lithographic resolution. Traditional, optical lithography has driven projection imaging to its physical limits, and a new, disruptive lithography technique is needed for continued growth of the semiconductor industry. The revolutionary S-FIL process is based on the fast, in-situ polymerization of a liquid imprint material in contact with a high-resolution mold or template. The templates, fabricated by direct-write lithography, present the greatest expense when implementing an S-FIL process in manufacturing; therefore, the template lifetime must be maximized to distribute costs over a large number of products. Degradable cross-linking materials allow imprint resist contaminated templates to be cleaned without the risk of inorganic residues becoming lodged on the template surface. Cured imprint resist is insoluble in all non-reactive solvents due to its highly cross-linked structure. A polymer contaminate may be rendered soluble by degrading the cross-links and reducing the molecular weight. Several degradable cross-linker candidates were examined for compatibility with S-FIL processing and utility for wafer imprint reworking and template cleaning. The properties of the imprint resists formulated with degradable cross-linkers are reported. Tertiary ester and acetal containing moieties were di-functionalized with acrylate groups to form S-FIL compatible and acid degradable imprint precursors. Both ester and acetal cross-linkers are neat, low-viscosity ([less than or equal to] 20 cP) liquids at room temperature and are miscible with common imprint precursor components. Classical gel theory predicts that greater than 99% de-cross-linking reaction conversion is necessary to achieve solubility in a cured imprint resist formulation with 10 wt% degradable cross-linker. Concentrated sulfuric acid and heat was used to successfully strip tertiary ester cross-linkers from wafer and model template surfaces. Acetal cross-linkers were demonstrated to strip in the presence of trifluoroacetic acid at room temperature. Three-dimensional patterning is an integral benefit of S-FIL, which enables the streamlining of dual damascene processing with the use of multi-level templates. Multi-level imprint patterning allows the removal of over 100 unit process steps from the fabrication of interconnect structures in a modern IC chip. Multi-level S-FIL can be integrated into existing copper damascene interconnect fabrication using two different strategies. One technique requires an imprint resist and etch process for transferring multi-level imprints into an industry standard low-k dielectric. Some of the considerations for designing the multi-level resist and etch process are briefly described. The second strategy leverages the broad variety and flexibility of the imprint materials set, which is not available in photoresist materials technology. New “functional” imprint materials may be used with multi-level S-FIL to produce interconnect structures by directly imprinting an interlayer dielectric (ILD) precursor. The challenges associated with introducing new dielectric materials into a copper damascene process are presented. The design, processing, characterization and integration of novel materials is documented. Multi-level S-FIL with a directly patternable dielectric (DPD) enables low-cost fabrication of interconnect structures in an IC manufacturing back end of line. DPD’s based on either sol-gel or benzocyclobutane and acrylate functionalized polyhedral oligomeric silsesquioxanes show promise for integration as ILD’s based on sufficient thermal and mechanical properties. Electrical test vehicle integration with sol-gel formulated DPD’s shows promising yield of interconnect structures with vias ranging from 2 to 0.12 [mu]m. Examination of interconnect structure revealed an acceptable via profile and sufficient contact with metal one for integration in IC devices.