|dc.creator||Wang, Wei-Shen, 1976-||en
|dc.description.abstract||The increased variability of process and environmental parameters is having a
significant impact on timing and power performance metrics of digital integrated circuits.
Traditionally formulated deterministic timing and power analysis algorithms based on
worst-case values of parameters often lead to over-pessimistic predictions, and may miss
actual worst-case performance corners. As a result, there is an increasing need for
statistical algorithms that can take into account the probabilistic nature of parameters.
The practical applications of statistical approaches, however, are restricted by the limited
availability of parameter distributions, and the idealized modeling of parameters adopted
in the statistical frameworks. In some cases, only partial probabilistic descriptions of
parameters are available, such as the mean and variance. Thus, designers are in an urgent
need for statistical approaches that can handle partially-specified uncertainty.
The objective of this dissertation is to provide robust and accurate timing and
power estimates for designers to assess the impact of variability on circuit performance.
This dissertation proposes a set of statistical analysis algorithms to estimate circuit timing
and leakage power dissipation based on robust probabilistic approaches and rigorous
mathematical modeling of parameter uncertainty. Full and partial probabilistic
descriptions of parameters can be incorporated into the developed statistical frameworks.
Specifically, the proposed approaches include: 1) a path-based statistical timing analysis
algorithm handling path delay correlations; 2) a statistical timing analysis algorithm
based on partial probabilistic descriptions of parameters; 3) analytical techniques for
assessing the impact of threshold voltage variation on leakage power of dual-threshold
voltage designs, and selecting optimal values of the threshold voltages for leakage power
reduction; and 4) a robust estimation algorithm for parametric yield and leakage
dissipation based on realistic descriptions of parameter uncertainty. The developed
algorithms along with the new modeling strategy effectively improve the overconservatism
of the corner-based deterministic algorithms, and also permit assessing the
impact of variability on circuit performance in the early design phase, which facilitates
fast power and timing verifications in the design process. As the magnitude of variability
continues to increase, the developed statistical algorithms and modeling strategy will
become increasingly important for the future technology generations.||
|dc.rights||Copyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.||en
|dc.subject||Digital integrated circuits--Design and construction--Statistical methods||en
|dc.subject||Electric leakage--Statistical methods||en
|dc.title||Models and algorithms for statistical timing and power analysis of digital integrated circuits||en
|dc.description.department||Electrical and Computer Engineering||en
|thesis.degree.department||Electrical and Computer Engineering||en
|thesis.degree.discipline||Electrical and Computer Engineering||en
|thesis.degree.grantor||The University of Texas at Austin||en
|thesis.degree.name||Doctor of Philosophy||en