Signal propagation modeling and optimization techniques for timing analysis
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In this dissertation we present two techniques with applications in the area of signal propagation and optimization for timing analysis. First we present a new buffer insertion technique for concurrent timing and interconnect optimization (Libra), based on an iterative sub-space minimization algorithm. Libra generates buffer configuration solutions that satisfy the timing constraints and minimize the implementation costs such as power consumption, buffer area, and routing resources like wire width and metal layer. In contrast to existing techniques that work at buffer node level, Libra partitions the routing tree into point-to-point paths allowing more efficient buffer configurations over long distances. The optimization algorithm does not depend on the specific procedure used to generate buffer configurations at path level which, as a consequence, can be customized for accuracy, speed, or specific technology. The path based solution selection also solves the problem of signal rise time propagation of earlier methods. Another advantage over existing algorithms is that our approach satisfies both early mode and late mode timing constraints. The second technique is a method to generate nonlinear timing models for logic gates. In our modeling approach, the timing characterization measurements data is the known solution of a differential equation representing the charging of the output port load by the unknown model. Using a variation of the Galerkin finite elements method, we model the differential equation and solve for the parameters of the model. Due to the use of finite elements, our modeling technique allows control of the accuracy and the stability of the models. We can list several advantages for our macromodels in comparison to the timing models generated by existing techniques: propagation of input signals with inductive ringing or noise perturbations without truncations, simulation of the effect of injected currents due to noise at the output port during gate switching, simulation of nets with multiple sources, and the models are reusable since they are valid for large ranges of input signals and output loads, the models are re-usable.