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Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias
(2010-06)
Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently threedimensional (3-D) integration with ...
Stress-Induced Delamination Of Through Silicon Via Structures
(2011-09)
Continuous scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32 nm technology node in microelectronics. Recently three-dimensional (3-D) integration with ...