Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in ...

We investigate the temperature-dependent resistivity of single-crystalline films of LaxLu1-xAs over the 5-300 K range. The resistivity was separated into lattice, carrier and impurity scattering regions. The effect of ...

Using current-sweep measurements, the set process in SiOx-based resistive random access memory (RRAM) has been found to consist of multiple resistance-reduction steps. Variation in set behaviors was observed and attributed ...

An edge-free structure and hermetic encapsulation technique are presented that enable SiOx-based resistive random-access memory (RRAM) operation in air. A controlled etch study indicates that the switching filament is close ...

A nanoindentation system was employed to characterize mechanical properties of silicon nanolines (SiNLs), which were fabricated by an anisotropic wet etching (AWE) process. The SiNLs had the linewidth ranging from 24 nm ...

We report the electrical characteristics of chemical vapor deposited (CVD) monolayer molybdenum disulfide (MoS2) top-gated field-effect transistors (FETs) on silicon nitride (Si3N4) substrates. We show that Si3N4 substrates ...

Plasma damage to low k dielectric materials was investigated from a mechanistic point of view. Low k dielectric films were treated by plasma Ar, O-2, N-2/H-2, N-2 and H-2 in a standard RIE chamber and the damage was ...

In this work, the effect of electron-electron scattering on spin transport in single layer graphene is studied using semi-classical Monte Carlo simulation. The D'yakonov-P'erel mechanism is considered for spin relaxation. ...

We study a reaction diffusion model which describes the formation of patterns on surfaces having defects. Through this model, the primary goal is to study the growth process of Ge on Si surface. We consider a two species ...

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with ...