Development of an innovative fabrication method for n-MOS to p-MOS tunable single metal gate/high-[kappa] insulator devices for multiple threshold voltage applications

Aggressive scaling required to augment device performance has caused conventional electrode materials to approach their physical scaling limits. Alternative metal gate/high dielectric constant (MG/High-[kappa]) stacks have been implemented successfully in commercial devices and hold promise for further scaling based performance advances. Existing MG/High-[kappa] technology does not achieve a single metal n-MOS to p-MOS effective work function (EWF) tuning range suitable for bulk silicon (Si) device applications. Dual metal gates (DMGs) utilizing a separate metal for n-MOS and p-MOS electrodes increases the cost and complexity of fabrication. The research presented herein introduces a method by which the cost and complexity of MG/High-[kappa] device fabrication may be reduced. Innovative fin field effect transistors (FinFETs) incorporating 3 dimensional ultra thin body silicon on oxide (3-D UTB-SOI) technology display superior electrical characteristics compared to bulk Si devices at the nanometer (nm) dimension and require only a +/-200meV n-MOS to p-MOS EWF tuning range around the Si mid-gap. Single metals capable of achieving this +/-200meV EWF tuning range have been evaluated herein and the tuning mechanisms investigated and engineered to develop a single MG/High-[kappa] FinFET the fabrication complexity of which is reduced by 40%. More specifically, the research shows that the metal thickness of titanium nitride/hafnium silicon oxide (TiN/HfSiOx) gate stack may be engineered to achieve an n-MOS (thinner TiN) to p-MOS (thicker TiN) appropriate FinFET EWF tuning range. FinFETs may be fabricated by depositing a single p-MOS appropriate TiN thickness which may be selectively etched back to achieve thinner, n-MOS appropriate films. Similar electrical behavior is exhibited by etched back and as deposited TiN electrode FinFETs. The single metal etch back fabrication method removes many of the additional steps required for DMG fabrication and preserves the integrity of the MG/High-[kappa] interface between n-MOS and p-MOS devices. These advantages result in reduced fabrication complexity and improved reliability and reproducibility.