Testing of delay lines in synchronizers

Abstract

With increasing complexity and speed of System-on-chip (SOC) designs, asynchronous design has become common among digital designers. Synchronous-asynchronous interactions will emerge as a key issue in future SOC designs. This poses test problems due to special modules employed in such interactions called synchronizers. Synchronizers have programmable delay lines, phase comparators along with analog modules like delay locked loops which make them hard to test. The present day solutions overlook testing of these modules which are crucial for the proper working of the synchronizer. This work presents a methodology to test delay lines for stuck-at faults and transition faults which were not considered during testing earlier