Modeling and design of paralleled SiC MOSFET for multi-chip power module

Silicon carbide (SiC) metal–oxide–semiconductor field effect transistors (MOSFETs) have seen rapid growth in recent years, thanks to its low conduction loss, fast switching speed, and good thermal conductivity. For high power applications, it is necessary to parallel two or more devices in order to achieve the desired current rating, conduction loss, and thermal performance. Traditional single-driver multi-chip module (SDM) requires strong drivers and suffers a lot from parasitic parameter mismatch induced transient current unbalance and intrinsic oscillation. To reduce the thermal imbalance and operation risks, the switching speeds of parallel MOSFETs or MOSFET modules in general are usually slowed with larger gate resistance, at the expense of higher switching loss. Therefore, this solution is not optimal since it indicates a poor utilization of the SiC MOSFET’s intrinsic high-speed capability. The research developed analytical models for the transient current sharing and inherent oscillation for two paralleled SiC MOSFETs’ switching process. The transient current sharing model is developed based on linearized circuit state equations, while the intrinsic oscillation model is based on small-signal equivalent circuits. By using these models, the influences of parasitic parameters are investigated. The optimized gate resistor selection to compensate circuit mismatches is discussed. Based on the studies and models, a 650 V, 300 A double-side cooling GaN HEMT based SDM is designed and fabricated. A better configuration of the multi-driver multi-chip module (MDM) is proposed and the performances are compared. The analytical models provide a fast way to evaluate and optimize the design or approach of any paralleled MOSFET cases. The proposed MDM solution could be a more efficient, more reliable power module design configuration. The parameter influence and comparison results were verified in the experimental tests.