Prevention of tri-state contention during scan using built-in constraint resolution

Abstract

Many modern circuits contain logic which must be controlled with mutually exclusive (one-out-of-n) control signals. Common examples include controls to 3-state buses and pass-gate multiplexers. If these control signals are allowed to attain any value combination other than one-out-of-n, the controlled logic may produce an unknown (X) state. In a scan based design, these mutually exclusive signals become problematic if they must be stored in latches. Mutually exclusive values will typically not be maintained on the outputs of these latches during scanning, nor as final values if random test patterns are scanned in. A new scan circuit construction obviates Automatic Test Pattern Generation (ATPG) constraints for the prevention of tristate contention on internal tristate buses and one-hot multiplexers. The circuit is supported by enhanced ATPG. The approach is to provide an alternative scan flipflop and design augmentation for instances where the flop is to be member of a set of constrained flops