Testability and fault modeling of partially depleted silicon-on-insulator integrated circuits
MetadataShow full item record
Partially Depleted Silicon-On-Insulator (SOI) technology has garnered more attention with regards to replacing traditional bulk silicon technology as the mainstream technology of choice for high performance / low power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the source and drain junction capacitance as well as a reduction in the traditional back biasing resulting from the body effect. The reported performance increases have been between 20 and 35%. However, this increase in performance comes at a cost of complexity from the test perspective. Where the SOI transistor is faster than the bulk transistor, there exists a variation in delay caused by threshold voltage shifts that must be accounted for at test. Additionally, new leakage sources exist due to the parasitic bipolar transistor that is inherent in every SOI MOSFET. This dissertation explores these issues, proposes test techniques, and describes a comprehensive transistor fault analysis that measures the effectiveness of different test techniques – both traditional and proposed – in the context of this promising technology.