Ultra thin HfO₂ gate stack for sub-100nm ULSI CMOS technology
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The scaling of the device feature sizes has led the progress in MOS integrated circuit technology. As the gate length of MOSFET is scaled down, the thinner gate oxide is required to reduce the short channel effects and maintain gate controllability over the channel with higher drive current capability. For the production of advanced CMOS devices in the sub 100nm regime, the continue reduction in the gate dielectric film thickness is one of the most essential issues that will limit future CMOS scaling. According to the SIA road map (Table1), the thickness of gate oxide should be ~10Å for 70nm technology generation by year 2008. The thermally grown silicon dioxide or nitrided silicon oxide have been typically used as the gate dielectric in MOS devices. However, as the thickness of the gate dielectric is decreased, gate leakage current due to direct tunneling reaches acceptable limits of many applications. The many alternate gate dielectric materials with high dielectric constant have been investigated intensively to replace SiO2. Recently, HfO2 films have received considerable attention as the most promising gate dielectric material due to its thermal stability with silicon and high dielectric constant with reasonable band alignment to silicon. The purpose of this work is to develop a detailed process for RTCVD (Rapid Thermal Chemical Vapor Deposition) HfO2 gate stack and to demonstrate the electrical and chemical properties of HfO2 gate stack for future technology generation. In addition, the possibility of direct insertion of HfO2 gate stack into conventional dual gate CMOS process is also investigated by fabrication and characterization of MOSFETs with n+/p+ poly silicon gate electrode.