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Models and algorithms for statistical timing and power analysis of digital integrated circuits
The increased variability of process and environmental parameters is having a significant impact on timing and power performance metrics of digital integrated circuits. Traditionally formulated deterministic timing and ...
Nanometer VLSI placement and optimization for multi-objective design closure
In a VLSI physical synthesis flow, placement directly defines the interconnection, which affects many other design objectives, such as timing, power consumption, congestion, and thermal issues. With the scaling of ...
Statistical algorithms for circuit synthesis under process variation and high defect density
As the technology scales, there is a need to develop design and optimization algorithms under various scenarios of uncertainties. These uncertainties are introduced by process variation and impact both delay and leakage. ...