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dc.contributor.advisorHo, P. S.en
dc.creatorRhee, Seung-hyunen
dc.date.accessioned2011-04-04T14:51:04Zen
dc.date.available2011-04-04T14:51:04Zen
dc.date.issued2001-08en
dc.identifier.urihttp://hdl.handle.net/2152/10811en
dc.descriptiontexten
dc.description.abstractThermal stress characteristics of high performance interconnects, including Al(Cu)/low-k, Cu/oxide and Cu/low-k, were investigated in order to understand the effects of material properties, interconnect geometry, process condition and interconnect structure on the stress behaviors. Xray diffraction method was employed to evaluate the stress behaviors of the interconnects during thermal cycling. Finite element analysis was performed to verify the X-ray measurements and to further investigate the stress characteristics. Submicron Al(Cu) and Cu interconnects investigated in this study behaved elastically within the temperature range of interest due to high yield strength of the thin lines. Low-k passivated Al(Cu) lines showed significantly decreased stress levels compared to the TEOS passivated lines with compressive stress in the direction normal to the surface near room temperature. This stress behavior was attributed to high CTE of the low-k dielectric material and the effect of low-k dielectric on Al(Cu) interconnect reliability was discussed. The stress characteristics of TEOS passivated Cu lines were similar to that of Al(Cu) lines. The lines showed very high triaxial stress levels after being cooled down due to high modulus of Cu. The large hydrostatic stress observed in the TEOS passivated Cu lines suggests that the stress induced void formation can still be a reliability concern in Cu interconnects. Lines with different aspect ratios were studied and the effect of line geometry on the stress behaviors was also discussed. Thermal stress characteristics of low-k passivated Cu lines were quite different from those of Al(Cu) lines. The lines exhibited tensile stresses in all principal directions including normal to the surface, indicating that the diffusion barrier plays an important role in controlling the stress behaviors of low-k passivated Cu lines. The effect of the barrier layer and its thickness was investigated using finite element analysis. The effect of line geometry was also evaluated both experimentally and by numerical calculations and the implications on the reliability of low-k passivated Cu interconnect were addressed.
dc.format.mediumelectronicen
dc.language.isoengen
dc.rightsCopyright is held by the author. Presentation of this material on the Libraries' web site by University Libraries, The University of Texas at Austin was made possible under a limited license grant from the author who has retained all copyrights in the works.en
dc.subjectSemiconductorsen
dc.subjectIntegrated circuitsen
dc.subjectSystem failures (Engineering)en
dc.titleThermal stress behaviors of Al(Cu)/low-k and Cu/low-k submicron interconnect structuresen
dc.description.departmentMaterials Science and Engineeringen
thesis.degree.departmentMaterials Science and Engineeringen
thesis.degree.disciplineMaterials Science and Engineeringen
thesis.degree.grantorThe University of Texas at Austinen
thesis.degree.levelDoctoralen
thesis.degree.nameDoctor of Philosophyen
dc.rights.restrictionRestricteden


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