• DRAM-aware prefetching and cache management 

      Lee, Chang Joo, 1975- (2010-12)
      Main memory system performance is crucial for high performance microprocessors. Even though the peak bandwidth of main memory systems has increased through improvements in the microarchitecture of Dynamic Random Access ...
    • Efficient runahead execution processors 

      Mutlu, Onur (2006)
      High-performance processors tolerate latency using out-of-order execution. Unfortunately, today’s processors are facing memory latencies in the order of hundreds of cycles. To tolerate such long latencies, out-of-order ...
    • Fair and high performance shared memory resource management 

      Ebrahimi, Eiman (2011-12)
      Chip multiprocessors (CMPs) commonly share a large portion of memory system resources among different cores. Since memory requests from different threads executing on different cores significantly interfere with one ...
    • Network-on-chip architectures for scalability and service guarantees 

      Grot, Boris (2011-08)
      Rapidly increasing transistor densities have led to the emergence of richly-integrated substrates in the form of chip multiprocessors and systems-on-a-chip. These devices integrate a variety of discrete resources, such as ...