Browsing by Subject "Transmitter"

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Design of linear transmitters for wireless applications
(2016-05-18) Ock, Sungmin; Gharpurey, Ranjit; Abraham, Jacob; Aziz, Adnan; Orshansky, Michael; Rudell, Jacques
Wireless standards for high data-rate communications typically employ complex modulation schemes that have large peak-to-average power ratios (PAPR), along with a significant bandwidth requirement. Transmitters for such applications often employ off-chip power amplifiers (PAs), that are typically operated in back-off, such that the peak output power is less than the output 1-dB compression point (P1dB), in order to minimize distortion. In mobile systems, architectures that can enhance the linearity of the transmit chain are highly attractive since these can reduce the PA's back-off requirement, which helps to enhance efficiency. In this dissertation, linearization techniques for mobile transmitters are explored. A Cartesian feedback-feedforward transmitter is proposed for linearity enhancement. The transmit path in the architecture is placed in a Cartesian feedback loop. The feedback error signal is applied to a Cartesian feedforward path for further linearity improvement. Linearity of the feedback-feedforward system is analyzed by using a Volterra series representation. System simulations using two-tone signals and modulated signals are also presented and are used to verify the linearity enhancement provided by the proposed architecture. A prototype transmitter IC that employs the Cartesian feedback-feedforward approach is implemented in a 0.13 μm CMOS process. Design considerations for critical transmitter circuits are discussed. A proof-of-concept Cartesian feedback-feedforward architecture that includes the prototype IC and external components is demonstrated. The implementation allows for a 8.7 dB improvement in the adjacent channel leakage ratio (ACLR), compared to an open-loop transmitter, for an output power of 16.6 dBm at 2.4 GHz while employing a 16-QAM LTE signal with 1.4 MHz bandwidth. The linearity of the Cartesian feedback-feedforward system is found to depend primarily on the loop gain of the Cartesian feedback and the linearity of the Cartesian feedforward path, which introduces a trade-off with power consumption. To enhance the linearity of the Cartesian feedback-feedforward transmitter even further within the Cartesian feedback loop, two modified Cartesian feedback-feedforward architectures are explored. System simulations show that both modified configurations can help to enhance linearity compared to the above Cartesian feedback-feedforward transmitter.
High performance pulse width modulated CMOS class D power amplifiers
(2012-12) Lu, Jingxue; Gharpurey, Ranjit
The objective of this research is to explore circuit techniques and architectures suitable for implementation in digital technologies, that can be used to enhance the efficiency of power stages. Specifically, the use of switching power stages with pulse-width modulation techniques is considered. Switching power stages, such as Class D amplifiers, are inherently well-suited for implementation in deep-submicron CMOS. Pulse-width modulation (PWM) employs discrete amplitude levels and encodes signal information in local time-based averages, and as such can also benefit from such technologies. Additionally PWM does not suffer from quantization noise, and is well-suited for low noise applications. PWM designs, that can be applied for a range of signal bandwidth requirements, spanning several tens to hundreds of kHz are proposed. Applications for these architectures include audio systems, powerline communications and wireless communications. Design challenges and requirements that can arise in different application contexts are considered in the specification of the architectures. A common goal in the definition of the architectures is to minimize complexity of the designs. In the first part of the dissertation, a third-order self-oscillating PWM class-D amplifier for audio applications, that utilizes a hysteretic comparator is described. The design is analyzed and its THD is theoretically determined by employing an equivalent model, that relates the approach to natural sampling pulse-width modulation. The architecture eliminates the requirement for a high-quality carrier generator. A low-cost hysteresis compensation technique is utilized to enhance distortion performance at high output power levels. An implementation is presented in a 0.7um CMOS process. The design achieves a dynamic range (DR) of 116.5 dB, and a THD+N of 0.0012%, while delivering a power of 125 mW into an 8[Omega] load at 1 kHz. The THD+N is under 0.006% up to 90% of the maximum output power. The amplifier can deliver 1.45 W into the load with a THD of 5% with a 5 V power supply. The efficiency is greater than 84% for output power larger than 1 W. The area of the amplifier is 6 mm². The achieved performance indicates that the design is well-suited for high-performance audio applications. A class D line driver that utilizes a phase-locked loop (PLL) based PWM generation technique is presented next. The principle of operation, and implementation details relating to loop stability, linearity and noise performance are analyzed. An implementation is presented in a 130nm CMOS process. The amplifier can deliver 1.2 W into an 6.8[Omega] load with a 4.8 V power supply. The architecture eliminates the requirement for a high-quality carrier generator and a fast, continuous voltage comparator that are often required in PWM implementations. The design can achieve a THD of -65 dB, with a switching frequency that can be as high as 20 MHz. The peak efficiency is 83% for output power larger than 1 W, for a switching frequency of 10 MHz. The area of the amplifier is 2.25 mm². This architecture is potentially suitable for powerline applications. Finally, a phase-locked loop based PWM Cartesian transmitter with the capability to drive switched power amplifiers, such as a Class D power amplifier, is proposed. A phase-locked loop based technique is employed to generate a high-frequency PWM pulse stream centered at 1.28 GHz. The prototype is simulated in a 130 nm CMOS process, and achieves 35% peak efficiency for 17 dBm output power with a carrier frequency of 900 MHz. Operation of the architecture with non-constant envelope modulation, such as that employed in the WCDMA standard, is verified in simulation.
Wideband receiver and transmitter architectures employing pulse width modulation
(2019-12-06) Kang, Heechai; Gharpurey, Ranjit; Abraham, Jacob; Orshansky, Michael; Kulkarni, Jaydeep; Pullela, Raja
Pulse width modulation (PWM) is an attractive signaling method since it can represent an analog signal while using a discrete-level signal, and is hence more robust to amplitude-noise than a purely analog signal. In addition, PWM can be utilized with switching circuits and thus can benefit from performance and area enhancements that result from process scaling. Receiver and transmitter architectures employing PWM are presented in this work. Architectures to generate high-frequency PWM for representing a wide-bandwidth modulated signal are proposed. A harmonic rejection (HR) receiver that utilizes PWM to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated in Chapter 2. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR by employing multiphase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth and seventh LO harmonics. Gain control using LO-path pulse-width control is demonstrated. The design is implemented in a 40-nm CMOS process. The measured receiver gain with HR is 26.4–30.1 dB in a multi-phase LO configuration and 28–31.8 dB in a single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst-case HR3 and HR5 ratios of 47 and 49 dB without calibration for f[subscript LO] = 100 MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) greater than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR on input signal amplitude is studied. In Chapter 3, a HR downconverter that can provide higher PWM-LO frequencies, in the range of approximately a GHz, is proposed. The approach employs current-mode operation, and significantly improves performance for narrow pulse-widths, which allows for high-frequency operation. The use of an input transconductor-cell with switches in the signal-path decreases the sensitivity of the HRR to harmonic power level. The design is simulated in a 65-nm CMOS technology, and shows HRRs of nearly 60-70 dB for the 3rd and 5th harmonics, with a 1 GHz LO, over a range of harmonic power levels, and rise and fall times of the PWM waveform. In Chapter 4, a delay-locked loop (DLL) based RF-PWM generator is proposed that can provide RF-PWM in response to broadband signals. The approach can be utilized in a Cartesian transmitter in combination with a switching output stage. The proposed transmitter architecture is verified in a macro-model simulation, using a signal bandwidth of 40 MHz, at a carrier frequency of 2 GHz. In Chapter 5, a Cartesian quadrature power amplifier (QPA) architecture that employs RF-PWM with a switched-capacitor (SC) class-D output stage is described. IQ combining is performed using the SC output stage. Amplitude modulation is performed using RF-PWM, instead of using capacitor ratios in the switched-capacitor combiner, thereby avoiding quantization noise. Outphasing is utilized to synthesize RF-PWM, which alleviates distortion due to narrow pulse-widths in the switching stage. Loss mechanisms in the SC combiner are identified and analyzed. AM-to-AM distortion in the proposed design arises due to resistance variation of the class-D switches. This distortion mechanism is analyzed and demonstrated by means of simulation in a 65-nm CMOS technology. The final part of the thesis (Chapter 6) introduces a Cartesian transmitter that uses of combination of the DLL-based outphasing modulator and switched-capacitor combiner for implementation of a wideband transmitter. An outphasing signal is generated to implement RF-PWM. Full amplitude modulation is achieved while varying the duty-cycle of the RF-PWM generator from 25%-75%, which significantly relaxes the narrow-pulse limitation observed in PWM signaling. The use of the phase detectors synchronized to the two clocks whose phase difference is in quadrature at the PWM frequency enhances the frequency response of the output of the transmitter. The IQ combiner employs a switched-capacitor design, described in Chapter 5. The Cartesian transmitter is implemented in a 65-nm CMOS process. The measured peak output power of the transmitter is 15.5 dBm and the design is verified with digitally-modulated signals with a bandwidth of up to 160 MHz