Browsing by Subject "Semiconductors--Testing"

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HDL slicing for verification and test
(2003) Vedula, Vivekananda Murthy; Abraham, Jacob A.
The semiconductor industry has been increasingly relying on computer-aided design (CAD) tools in order to meet its demand for high performance and stringent time-to-market requirements. However, practical application of state-of-the-art CAD tools is severely limited by the sheer size of the design sizes. Therefore, an appropriate methodology that exploits the inherent modular structure within the complex designs, is desired. This dissertation proposes such a methodology that is useful with a variety of CAD tools in design verification and manufacturing test generation. Functional test generation using sequential automatic test pattern generation (ATPG) tools is extremely computation intensive and produces acceptable results only on relatively small designs. Therefore, hierarchical approaches are necessary to reduce the ATPG complexity. A promising approach was previously proposed in which individual modules in a design are targeted one at a time, using an ad-hoc abstraction for the reminder of the design derived from its register-transfer level (RTL) model. Based on this approach, an elegant and a systematic approach based on “program slicing”, that allows it to be scalable for large designs, is developed. The theoretical basis for applying program slicing on hardware description languages (HDLs) is established, and a tool called FACTOR has been implemented to automate the approach for test generation and testability analysis. Design verification requires exploring the complete design space to ensure the correctness of the design. A proof-by-contradiction approach called bounded model checking (BMC) has been proposed, which utilizes satisfiability (SAT) capabilities to find counterexamples for temporal properties within a specified number of time steps. The proposed scheme harnesses the power of sequential-ATPG tools to use structural information of a hardware design, to perform BMC more efficiently. This approach has been further augmented by the HDL slicing methodology for test generation, to accelerate the verification methodology. Symbolic simulation uses symbols rather than actual values for simulating a hardware design, so that the responses to a class of values can be computed and checked for correctness in a single run. The effectiveness of this approach has been incorporated into a powerful verification methodology, called symbolic trajectory evaluation (STE), to verify properties of bounded state sequences, intermixed with properties of invariant behavior. Assertions are described in a limited form of temporal logic and are symbolically validated against the design under verification. The HDL slicing tool, FACTOR, has been appropriately applied to speed up the verification of the floating point adder-subtractor unit of the Pentium 4 design in Intel’s Forte verification framework.
New test vector compression techniques based on linear expansion
(2004) Chakravadhanula, Krishna V.; Touba, Nur A.
This dissertation considers the problem of reducing the storage as well as the bandwidth (data transfer rate between tester and chip) requirements of automatic test equipment (i.e., testers). Several new test vector compression schemes based on linear expansion are presented. The compressed test vectors are stored on the tester and transferred to the chip where a linear expansion network is used to decompress them. The lossless compression techniques described here significantly reduce the test data stored on the tester compared with conventional external testing, but do not require the hardware overhead and complexity of full stand-alone built-in self-test (BIST). One of the contributions of this dissertation is efficient compression techniques that do not require any constraints on the automatic test pattern generation (ATPG) process, thus simplifying the design flow. A new form of linear feedback shift register (LFSR) reseeding is described which allows partial dynamic reseeding and achieves greater encoding efficiencies than previous forms of LFSR reseeding. A new hybrid BIST scheme is proposed that uses an “incrementally guided LFSR” to provide very attractive tradeoffs between test length and tester storage requirements while using very simple vii on-chip hardware. A technique is described that combines LFSR reseeding and statistical coding in a powerful way by taking advantage of the large solution space of linear equations to find LFSR seeds that can be efficiently encoded using a statistical code. A new scheme for combinational linear expansion is proposed that uses adjustable width expansion to eliminate the need that every scan bit-slice be in the output space of the linear decompressor, while providing greater compression than fixed width expansion techniques. Finally, a compression scheme is described that combines three different stages of linear expansion to achieve extremely high encoding efficiencies while requiring low hardware overhead as it configures the decompressor out of the scan cells themselves. Both the adjustable width and 3-stage decompression schemes provide the nice feature that any scan vector can be efficiently compressed regardless of the number or distribution of specified bits, thus allowing the use of any ATPG procedure without any constraints.