Browsing by Subject "Process variation"

Now showing 1 - 4 of 4

Compensating process and temperature variation in 32nm CMOS circuits with adaptive body bias
(2010-05) Tariq, Usman, 1982-; Flake, Robert H.; Orshansky, Michael E.
As we scale down each process generation the degree of control we have on device parameters decreases. We are left to contend with a great deal of variability in process and environmental parameters. Process variation impacts dopant concentration, channel length, oxide thickness and other device parameters. Temperature variation too affects several parameters, amongst them are the threshold voltage and carrier mobility. All of these variations can either be margined for during design or compensated for dynamically. In this paper the technique of adaptive body bias is successfully applied to compensate for the variation in design so that the circuit operates at no more than 10 percent of the optimal pvt (process voltage temperature) point while minimizing leakage.
Improving energy efficiency of reliable massively-parallel architectures
(2012-05) Krimer, Evgeni; Erez, Mattan; John, Lizy K.; Orshansky, Michael; Gerstlauer, Andreas; Sentis, Luis
While transistor size continues to shrink every technology generation increasing the amount of transistors on a die, the reduction in energy consumption is less significant. Furthermore, newer technologies induce fabrication challenges resulting in uncertainties in transistor and wire properties. Therefore to ensure correctness, design margins are introduced resulting in significantly sub-optimal energy efficiency. While increasing parallelism and the use of gating methods contribute to energy consumption reduction, ultimately, more radical changes to the architecture and better integration of architectural and circuit techniques will be necessary. This dissertation explores one such approach, combining a highly-efficient massively-parallel processor architecture with a design methodology that reduces energy by trimming design margins. Using a massively-parallel GPU-like (graphics processing unit) base- line architecture, we discuss the different components of process variation and design microarchitectural approaches supporting efficient margins reduction. We evaluate our design using a cycle-based GPU simulator, describe the conditions where efficiency improvements can be obtained, and explore the benefits of decoupling across a wide range of parameters. We architect a test-chip that was fabricated and show these mechanisms to work. We also discuss why previously developed related approaches fall short when process variation is very large, such as in low-voltage operation or as expected for future VLSI technology. We therefore develop and evaluate a new approach specifically for high-variation scenarios. To summarize, in this work, we address the emerging challenges of modern massively parallel architectures including energy efficient, reliable operation and high process variation. We believe that the results of this work are essential for breaking through the energy wall, continuing to improve the efficiency of future generations of the massively parallel architectures.
Refactoring-based statistical timing analysis and its applications to robust design and test synthesis
(2011-05) Chung, Jae Yong, 1981-; Abraham, Jacob A.; Touba, Nur A.; Aziz, Adnan; Orshansky, Michael; Zhan, Yaping
Technology scaling in the nanometer era comes with a significant amount of process variation, leading to lower yield and new types of defective parts. These challenges necessitate robust design to ensure adequate yield, and smarter testing to screen out bad chips. Statistical static timing analysis (SSTA) en- ables this but suffers from crude approximation algorithms. This dissertation first studies the underlying theories of timing graphs and proposes two fundamental techniques enhancing the core statistical timing algorithms. We first propose the refactoring technique to capture topological correlation. Static timing analysis is based on levelized breadth-first traversal, which is a fundamental graph traversal technique and has been used for static timing analysis over the past decades. We show that there are numerous alternatives to the traversal because of an algebraic property, the distributivity of addition over maximum. This new interpretation extends the degrees of freedom of static timing analysis, which is exploited to improve the accuracy of SSTA. We also propose a novel operator for computing joint probabilities in SSTA. In many SSTA applications, this is very common but is done using the max operator which results in much error due to the linear approximation. The new operator provides significantly higher accuracy at a small cost of run time. Second, based on the two fundamental studies, this dissertation devel- ops three applications. We propose a criticality computation method that is essential to robust design and test synthesis; The proposed method, combined with the two fundamental techniques, achieves drastic accuracy improvement over the state-of-the-art method, demonstrating the benefits in practical ap- plications. We formulate the statistical path selection problem for at-speed test as a gambling problem and present an elegant solution based on the Kelly criterion. To circumvent the coverage loss issue in statistical path selection, we propose a testability driven approach, making it a practical solution for coping with parametric defects.
Simultaneous statistical delay and slew optimization for interconnect pipelines
(2005-12-24) Havlir, Andrew Michael; Pan, David Z.
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is developed to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ignoring location dependent variation can cause timing yield loss of 8.8% in a delay limited circuit. Furthermore, the area of the circuit can be improved by over 10% when the location dependent variation and residual random variation are understood and separated. Lastly, experiment results show that sizing alone is not sufficient to optimize interconnect pipelines with location dependent variation. Under equivalent area, a circuit optimized with only sizing changes may violate the slew constraint on over 50% of the nets