Browsing by Subject "Microprocessors--Testing"

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Automatic generation of instruction sequences for software-based self-test of processors and systems-on-a-chip
(2008-05) Gurumurthy, Sankaranarayanan; Abraham, Jacob A.
At-speed functional tests are an important part of the manufacturing test flow of processors. With delay defects becoming more common due to the properties of the newer process technologies, at-speed functional tests have become indispensable. Traditionally, functional tests needed expensive automatic testing equipment due to the memory and speed requirements associated. This cost issue was solved by native-mode testing which uses the intelligence of the processor to test itself. In the native-mode self-test (also known as software-based self-test) paradigm, instruction sequences are loaded into the cache to test the processor for defects. Generally, only random instructions are used in nativemode tests. As with any random sequence based testing, there are faults that are left undetected by random instructions. Manual effort is necessary to generate the tests that can detect those faults, requiring a detailed knowledge of the instruction set architecture and the micro-architecture of the processor. We propose an automatic technique that alleviates the need for such manual effort. Our technique has a hierarchical approach. We use traditional automatic test pattern generation (ATPG) algorithms for generating tests at the local level (module or combinational blocks). These tests are mapped to instructions at the global level using a verification engine. We also have feedback between these two levels for more efficient testing. We demonstrate the technique on a publicly available processor. We then enhance the technique to test an entire system-on-a-chip (SOC). A typical SOC has an embedded processor. We use this embedded processor to test the other blocks in the SOC. In general, most of these blocks are designed by the design reuse methodology. Therefore, these blocks may be available only as black-boxes. Our technique is well suited to test such blocks. We use existing test vectors for the core and present a technique that generates instruction sequences that when executed by the processor generates the given vectors at the boundaries of the blocks. We designed an SOC using an ARM core and a publicly available encryption core and experimented on it to demonstrate the effectiveness of our technique.
Test generation for realistic defects
(2003) Krishnamachary, Arun; Abraham, Jacob A.
The rapidly evolving process technologies and device complexity that have fueled the exponential growth in the performance of microprocessors have made the manufacturing test of these devices a hard problem. In addition to making the detection of defects modeled by the classical fault models like the stuck-at and the transition fault model more complex, these process technologies have resulted in additional types of defects (like the resistive opens, defects due to the process parameter variations and crosstalk defects) becoming more prominent. The requirement for an effective delay test framework which involves an effective fault model, optimized test generation procedure and efficient test application has become even more urgent in the current scenario. This framework also needs to address the issues with yield and complexity (due to the large number of faults) that are associated with a delay test strategy. In this dissertation, we provide a strategy to help address many of the issues outlined above. An improved delay fault model is first proposed which enables better detection of resistive open defects and also yields a good oppurtunistic coverage of defects due to process parameter variations. This is coupled with an optimized test generation strategy, which facilitates efficient delay test generation under the fault model. A fault collapsing technique helps reduce the number of faults that need to be targeted. To improve the yield of a scan based test application, a technique is provided to identify the functional sensitizability of paths across multiple latch boundaries, and the effect of this strategy on yield is then calculated. Finally a technique to enable use of ATPG to evaluate the chip level sensitizability of paths which enables the use of tighter timing bounds in chips is presented.