Browsing by Subject "Microprocessor simulation"

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Accurate microprocessor simulation via performance profiling
(2006-12) Olsen, Tyler Dane; Burger, Doug, 1969-
Fast and accurate microprocessor simulation has long remained a challenge in the design and evaluation of new microprocessors. This problem only continues to exacerbate as underlying microarchitectures become more complicated and slow down simulation speed further, while the code size of popular benchmark suites continues to explode exponentially. Many techniques have been proposed and put into use to reduce simulation cost while maintaining a high degree of accuracy, but no technique is perfect and even the most popular and accurate approaches suffer from severe drawbacks. In this thesis, I propose a different approach by a simulation methodology, which I call PerfPoint, that profiles the performance of benchmarks running on existing hardware, and using those performance profiles to extract small intervals of instructions from the code stream. Simulating these instruction segments, or perfpoints, and weighting the results by the amount of the benchmark that each is intended to represent results in very accurate results at a minimal simulation cost. The collected performance data is dependent on the microarchitecture and susceptible to various sources of noise. The reliance of the simulation methodology on this data as a foundation is a grave concern. Much of this thesis is dedicated to quantifying the negative effects present in this data as well as building a case for the acceptable use of this data as a basis for a simulation methodology. The PerfPoint methodology is validated using multiple architectures, a large array of benchmarks, and a substantial number of configuration parameters for PerfPoint. I report that for the SPEC CPU 2000 integer benchmark suite, using my methodology results in less than [plus or minus]1% CPI error for all configurations of PerfPoint and all datasets used. These CPI percent error margins are obtained by simulating between 0.076% and 2.425% of the entire benchmark suite, depending on the PerfPoint configuration parameters that are used.
A microprocessor performance and reliability simulation framework using the speculative functional-first methodology
(2011-12) Yuan, Yi; Chiou, Derek; Erez, Mattan
With the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features throughput-oriented, latency-tolerant designs to cope with the challenges of the hybrid platform. Furthermore, a fault injection framework is added to this implementation that allows designers to study the reliability aspects of their processors. The result is a simulator that is fast, accurate, flexible, and extensible.