Browsing by Subject "Metal oxide semiconductor field-effect transistors--Materials"

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The effects of silicon, nitrogen and oxygen incorporation and oxygen-scavenging technique on performances of hafnium-based gate dielectric MOSFETs
(2006) Choi, Changhwan; Lee, Jack Chung-Yeung
The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV-1 cm -2), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. According to ITRS (International Technology Roadmap for Semiconductor) roadmap, the EOT (equivalent oxide thickness) in MOSFETs for next generation technology node must be below ~15Å for both high performance logic application like microprocessor and low power application such as mobile electronics. However, as the dramatic scaling-down is continuously needed, ultra thin silicon dioxide cannot be useful any more as a gate dielectric because the use of ultra thin SiO2 gate dielectrics gives rise to a number of problems, including high gate leakage current, reduced drive current, reliability degradation, B (boron) penetration, and the need to grow ultra thin and uniform layer. Especially, the physical limit and reliability problem of ulta thin SiO2 result from significantly increased direct tunneling current in such a thin region. Therefore, the need for new gate dielectric materials is emerging to reduce leakage current while maintaining a low EOT. Many materials with a dielectric constant higher than that of SiO2, known as high k dielectrics, have been being investigated in order to identify a SiO2 replacement. So far, HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The phase transformation due to crystallization of dielectric can provide the formation of gain boundary that will act as high oxygen or dopants diffusivity path, making EOT scaling problematic and causing device failure with high leakage current. Nitrogen incorporation into high k materials has been investigated to achieve further scaling and improve thermal and electrical stability because nitrogen is known to suppress oxygen diffusion, and reduce low k interfacial layer growth at the Si interface. However, nitrogen incorporation alone can result in several potential problems. Since nitrogen is likely to bind to Si, most of the nitrogen incorporated tends to pile up at the Si interface. This leads to an increased interface trapped charge density, increased hysteresis and lower channel mobility due to coulombic scattering. Also, the amount of nitrogen incorporated can be limited due to nitrogen out-diffusion during anneals. A potential solution to these problems is incorporating Si to modulate the nitrogen profile since Si traps nitrogen and suppresses nitrogen out-diffusion. In the first part of this study, the effects of nitrogen and silicon on Hf-based MOSFET performances and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen profile has been modulated by inserting Si layer into HfOxNy. Nitrogen incorporation enhanced Vth shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer. Although nitrogen incorporation reduces interfacial reaction and results in aggressive thinning such as EOT below10Å, which is required for beyond 65nm design rule, it also induces disadvantages such as higher hysteresis, higher charge trapping and degraded channel carrier mobility due to trap charges caused by nitrogen itself. Therefore, for aggressive scaling with good interface quality, novel process without using nitrogen, which can suppress low k interfacial regrowth, should be delivered. Some transition metals like Hf, Zr and Ti have very high oxygen solubility as well as negative free energy of oxide formation. These properties can be used to decompose SiO2 like low k interfacial oxide upon appropriate annealing (i.e., oxygen scavenging effect) and produce further EOT scaling. As for second part of this study, for highly scaled gate dielectric application, a novel oxygen scavenging approach has been proposed and investigated. A novel process has been developed to achieve ultra-thin gate dielectrics (EOT<0.7nm) without involving nitrogen incorporation by engineering interface oxide thickness. Interfacial oxide formation was suppressed by the “oxygen-scavenging effect” using Hf metal on underlying HfO2 device structure with appropriate annealing. The scavenging Hf metal layer consumes oxygen sources leading to further scaling still using undoped HfO2. Using this fabrication approach, EOT of ~0.9nm after conventional self-aligned MOSFET process was successfully obtained. In addition, further EOT improvement (EOT: 0.55~0.60nm) was realized in conjunction with nitrogen incorporation using scavenging effect. Excellent charge trapping and MOSFET characteristics have been demonstrated.
Evaluation of nitrogen incorporation effects in HfO₂ gate dielectric for improved MOSFET performance
(2003-12) Cho, Hag-ju, 1969-; Lee, Jack Chung-Yeung
The aggressive scaling of Si integration technology requires the thinning of SiO2 gate oxide. However, as the oxide thickness continues to decrease, the leakage current density becomes significantly excessive due to direct tunneling. Thus, high-k dielectric, which has a higher dielectric constant than SiO2, has been intensively studied for future I.C. application. Among various high-k dielectrics, HfO2 is considered to be the most promising candidate because it has a high dielectric constant ~25, large heat of formation, relatively large band gap ~6 eV, and is thermally stable with silicon, and appears to be compatible with Si processes. In this study, nitrogen incorporation in HfO2 has been studied for improving HfO2 device performance. Thermal nitridation of Si prior to HfO2 deposition is one of the methods for incorporating N. However, it resulted in degraded interface. Thus, top nitridation was explored to prevent oxygen and boron penetration into Si substrate while maintaining HfO2/Si interface. As a result of using HfON on HfO2, thermal stability and immunity to boron diffusion were improved. In addition, MOSFET device using the top HfON layer showed about 2 times higher drive current compared to HfO2. The improvement was enhanced by applying high temperature forming gas annealing at 600o C prior to Al metal deposition. However, it turned out that such advantages from the top HfON layer were very limited due to a very small amount of nitrogen (< 1%) To achieve higher nitrogen concentration at the top, HfSiON (k~12-16) was used. Nitrogen was incorporated in HfSixOy in a range of 12-28 at.%. None of nitrogen in the upper part of the dielectric diffused to the interface of HfO2 and Si substrate for anneals up to 800o C. Dielectric constant and crystallization temperature were found to increase as N increased. In addition to improved thermal stability and reduced boron diffusion, HfSiON/HfO2 (TSN) devices showed higher channel mobility and higher drive current compared to HfO2 devices. SiON interfacial layer between TSN and Si further reduced EOT without sacrificing hysteresis and Dit. Even higher nitrogen concentration at the top was achieved by NH3 annealing of TSN gate dielectric. The application of NH3 annealing to in-situ processed TSN resulted in EOT < 10 Å. The experimental results of this study suggest that nitrogen profile engineering for high-k materials is a promising technique to improve MOSFET performance.
Fabrication modeling and reliability of novel architecture and novel materials based MOSFET devices
(2006) Dey, Sagnik; Banerjee, Sanjay
As device dimensions are scaled beyond the 45nm node, new device architectures and new materials need to be examined which are able to address the technological challenges and meet the requirements for sub-50nm MOSFETs. In this dissertation an alternate MOSFET device architecture is proposed that is not only capable of excellent subthreshold characteristics and off-state leakage current but also enhanced drive currents leading to high ION/IOFF ratio that can make it a suitable candidate for replacing the planar MOSFET as scaling is extended beyond the 45nm CMOS technology node. The proposed MOSFET device is formed by a fully-depleted Si cantilever channel suspended between source/drain “anchors” wrapped all-around by the gate. The device architecture proposed is further integrated with a high-k dielectric and metal gate, making it more amenable to scaling. In addition to novel architectures, high mobility novel material based channel engineering has also emerged as an attractive alternative for performance enhancements beyond sub-50nm nodes. If such materials such as Ge, or SiGe or strained-Si are to be used in production they need to be integrated on Si substrates from the cost and manufacturability point of view, along with concomitant requirements of good material quality and simple processing. This dissertation describes a technique of epitaxially growing high quality pure Ge-on-bulk Si substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD). The Ge layer is grown on thin SiGe layers with rapidly-varying Ge mole fraction which have been shown to block misfit dislocation defects. A similar technique to implement biaxially-tensile-strained Si on ultra-thin dislocation blocking buffer layers is also demonstrated. NMOSFETs fabricated on the strained-Si channels showed significant enhancements in mobility. This dissertation also demonstrates integration of high-mobility SiGe with the fully-depleted gate-all-around cantilever channel architecture which might be suitable for high performance devices. Finally modeling and analysis of hot carrier reliability of strained Si devices is included for Intel’s 65nm and 90nm nodes, along with studies of low frequency noise degradation.
III-V channel MOS devices with atomic-layer-deposited high-k gate dielectrics : interface and carrier transport studies
(2008-12) Shahrjerdi, Davood, 1980-; Banerjee, Sanjay
The performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs.
Process development, characterization, transient relaxation, and reliability study of HfO₂ and HfSi(x)O(y) gate oxide for 45nm technology and beyond
(2005) Akbar, Mohammad Shahariar; Lee, Jack Chung-Yeung
Silicon CMOS technology has been advancing along an exponential path of aggressively shrinking device dimensions, increasing density, increasing speed, and decreasing cost. Although providing huge benefits in microprocessor performances, advances in technology are accelerating the onset of causing enormous challenges in device integration and reliability. With device miniaturization, device design and process errors are shrinking, which in turn impact device characteristics and reliability. To keep pace with aggressive scaling, CMOS conventional SiO2 gate oxide are facing tremendous challenges in power consumption and reliability. Aggressive scaling of SiO2 pushed the technology down to the limit of direct tunneling regime, where the gate oxide leakage current increases exponentially as the thickness decreases. Thus the high ix performance is coming from sacrificing both static and dynamic power of the circuits. Scaling up to 65nm technology node, use of SiO2 and SiOxNy based dielectric barely met the ITRS roadmap. But keeping the same architecture with the same material we can’t meet the 45nm technology gate oxide thickness and leakage current requirements. Therefore high-k dielectrics, of which HfO2 and their silicates are most promising candidates, have attracted a great deal of attention recently. However, high-k dielectrics have also faced lots of integration challenges and issues that are needed to be resolved carefully before pushing it in production. For example, bulk charge trapping, interface states, degraded mobility, growth of interfacial layer, low crystallization temperature, dielectric phase separation, fermi pinning, soft optical phonon scattering, remote coulomb scattering, pre-existing traps are among those issues. In this research, process development, characterization and reliability study of HfO2 and its silicate have been performed. It has been observed that both nitrogen (N) and chlorine (Cl) have significant effect in improving the device performances. Incorporation of nitrogen by NH3 post-deposition anneal reduced EOT (effective oxide thickness), and improved device characteristics, like Id-Vg, Id-Vd characteristics, and mobility. On the other hand, surface nitridation using NH3 was found to be an effective way to aggressively scale down the EOT. Moreover, Cl treatment using precursor, HfCl4 pulse time variation in ALD (atomic layer deposition) HfO2, and using HCl as high-k post deposition rinsing element, both mobility and bias instabilities of high-k oxides could be improved. Reliability of Hf-based oxide could be improved by compositionally varying HfSixOy structure. Fabricating Hf-silicate with low composition of Si on top of Hf silicate with high composition of Si not only enhanced the device performance, but also improved the reliability characteristics. Furthermore, insertion of Si in the HfOxNy dielectric was found to be an effective way to improve device performance and reliability. At the end, a novel approach in understanding the breakdown mechanism of HfO2 has been proposed by stress-anneal experiments. It was found that accumulation of holes is primarily responsible for breakdown of HfO2 under substrate injection condition. An appropriate model has also been proposed along with supporting experimental data. Considering all of the process development, characterization and reliability studies made in this research, it can successfully be asserted that high-k gate oxide can be proposed as a viable and promising candidate for 45nm technology and beyond. But still careful attention need to be taken to resolve remaining intrinsic and extrinsic issues in high-k gate oxide.
Semiclassical Monte Carlo simulation of nano-scaled semiconductor devices
(2007-05) Ghosh, Bahniman, 1971-; Banerjee, Sanjay; Register, Leonard F.
As the channel lengths of MOSFETs are being scaled down, the focus is on replacing silicon by high mobility channel materials, such as Ge and III-V semiconductors. This is because mobility and saturation velocity determine the on current of short channel MOSFETs. However, a priori, it is not possible to determine the material that will maximize the ratio of ON current to OFF current. Hence it is interesting to perform simulations to compare the performance of various semiconductor devices with their silicon counterparts. In this work, a semiclassical Monte Carlo simulator, Monte Carlo University of Texas (MCUT), has been used and modified to handle Ge and III-V MOSFETs. It is capable of handling full bandstructure and incorporates various scattering models, including, inelastic acoustic phonon scattering with longitudinal and transverse modes, optical phonon scattering, impact ionization, ionized impurity scattering, surface roughness scattering, remote Coulomb, remote surface roughness scattering and polar optical phonon scattering. Quantum correction in the inversion layer is taken into account in the form of a modified potential that reproduces the correct concentration of carriers. Germanium Nand PMOSFETs and GaAs and InP NMOSFETs seem to perform worse than their silicon counterparts when the saturation currents are compared at the same gate overdrive. The results on GaAs and InP NMOSFETs are considered preliminary at this stage.
A study of the performance and reliability characteristics of HfO₂ MOSFET's with polysilicon gate electrodes
(2002) Onishi, Katsunori; Lee, Jack Chung-Yeung
Aggressive scaling of CMOS integrated circuits requires continuous miniaturization of the MOS transistor structures, including gate dielectric thickness. Conventional SiO2 is reaching its physical limitations as an insulator in terms of gate leakage current, uniformity control, and reliability requirements. High-k gate dielectrics, which have higher dielectric constants (k) than that of SiO2, have attracted a great deal of attention in the past few years, because of their potential for reducing gate leakage current while keeping the equivalent oxide thickness (EOT) thin. HfO2 has emerged as one of the most promising candidates, since it possesses a dielectric constant of 22 – 25, a large band gap of 5.6 eV with sufficient band offsets of larger than 1.5 eV, and is thermally stabile in contact with silicon. In this research, HfO2 MOS devices with polysilicon gate electrodes were investigated. The HfO2 dielectric was found to be compatible with polysilicon gate electrode. Minimum EOT of ~12 Å was achieved for the control process and it was scaled down to ~10 Å by a surface nitridation (SN) technique with an NH3 annealing. Boron penetration was observed on the control HfO2 devices, but it was improved with the SN technique as well. On the other hand, the SN technique exhibited adverse effects such as the degradations in mobility and negative bias-temperature instability on PMOSFET’s. Although inadequate channel mobility was a concern for the HfO2 MOSFET’s, it was found that high-temperature (500 – 600°C) forming gas annealing (HT-FGA) was effective in improving the mobility as well as reducing interfacial state density. The improvement was further enhanced with surface NO annealing, but it increased the EOT value. With regard to the reliability characterizations, charge trapping due to gate voltage stress caused significant Vt shift on the HfO2 NMOSFET’s and could be a scaling limit of the dielectric. Deuterium (D2) annealing was found to be an excellent technique for suppressing the charge traps while maintaining the similar mobility enhancement as HT-FGA. Overall, HfO2 MOSFET’s with polysilicon gate electrodes demonstrated promising performance and reliability characteristics. The HfO2-based dielectrics deserve to be further investigated as the future high-k gate dielectric.
Technology development and study of rapid thermal CVD high-K gate dielectrics and CVD metal gate electrode for future ULSI MOSFET device integration : zirconium oxide, and hafnium oxide
(2003-05) Lee, Choong-ho; Kwong, Dim-Lee
CMOS technology has been so successful in improving device performance, shrinking device size and achieving good reliability. Based on the ITRS (International Technology Roadmap for Semiconductors), a premise of the Roadmap has been that continued scaling of microelectronics. The 2001 ITRS map showed highlights several challenges such as limitation of lithography, integration of complicate structures, introducing new material into the manufacturing, and shrinking of gate oxide thickness. The most challenging issue is the replacing silicon dioxide as a gate dielectric of MOSFET because it affects important transistor characteristics as well as device reliabilities. And the other issues for the device scaled less than 65nm are polysilicon gate depletion and quantum mechanical effect. CVD oxynitride or plasma nitridation of silicon dioxide will be used 90nm generation even though high dielectric gate materials have been investigated intensively. Because there are immense task still remained to integrate high–k material into manufacturing. This dissertation will present research on advanced gate dielectrics (zirconium oxide, and hafnium oxide) processed by MOCVD (Metal Organic Chemical Vapor Deposition) method that have been developed for ULSI MOSFET devices. Also CVD TaN as well as PVD TaN metal gate electrodes were studied for hafnium oxide gate electrode MOSFET application. And it is found that zirconium oxide is compatible with metal gate process and hafnium oxide is stable for both poly silicon and metal gate electrode. And furthermore refractive metal gate electrodes (TiN, TaN) were also demonstrated with both PVD and CVD method and found CVD metal gate electrode is more preferred for future generation MOSFET device.