Browsing by Subject "Metal oxide semiconductor field-effect transistors--Design and construction"

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Fabrication modeling and reliability of novel architecture and novel materials based MOSFET devices
(2006) Dey, Sagnik; Banerjee, Sanjay
As device dimensions are scaled beyond the 45nm node, new device architectures and new materials need to be examined which are able to address the technological challenges and meet the requirements for sub-50nm MOSFETs. In this dissertation an alternate MOSFET device architecture is proposed that is not only capable of excellent subthreshold characteristics and off-state leakage current but also enhanced drive currents leading to high ION/IOFF ratio that can make it a suitable candidate for replacing the planar MOSFET as scaling is extended beyond the 45nm CMOS technology node. The proposed MOSFET device is formed by a fully-depleted Si cantilever channel suspended between source/drain “anchors” wrapped all-around by the gate. The device architecture proposed is further integrated with a high-k dielectric and metal gate, making it more amenable to scaling. In addition to novel architectures, high mobility novel material based channel engineering has also emerged as an attractive alternative for performance enhancements beyond sub-50nm nodes. If such materials such as Ge, or SiGe or strained-Si are to be used in production they need to be integrated on Si substrates from the cost and manufacturability point of view, along with concomitant requirements of good material quality and simple processing. This dissertation describes a technique of epitaxially growing high quality pure Ge-on-bulk Si substrates by ultra-high-vacuum chemical vapor deposition (UHVCVD). The Ge layer is grown on thin SiGe layers with rapidly-varying Ge mole fraction which have been shown to block misfit dislocation defects. A similar technique to implement biaxially-tensile-strained Si on ultra-thin dislocation blocking buffer layers is also demonstrated. NMOSFETs fabricated on the strained-Si channels showed significant enhancements in mobility. This dissertation also demonstrates integration of high-mobility SiGe with the fully-depleted gate-all-around cantilever channel architecture which might be suitable for high performance devices. Finally modeling and analysis of hot carrier reliability of strained Si devices is included for Intel’s 65nm and 90nm nodes, along with studies of low frequency noise degradation.
Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition
(2006) Kelly, David Quest; Banerjee, Sanjay
After the integrated circuit was invented in 1959, complementary metal-oxidesemiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. viii Although not yet in production, high-κ dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicongermanium (Si1-xGex), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-κ dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strainrelaxed Si1-xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge1-yCy) layers on Si for the fabrication of MOS transistors with improved drive currents. By incorporating a small amount of C in Ge, the crystal quality of Ge epitaxial layers grown directly on Si can be dramatically improved. The Ge1-yCy layers have been used to fabricate high-drivecurrent p-MOSFETs with high-κ dielectrics and metal gates. In addition to the electrical results, materials-related experimental data was acquired and analyzed to provide insights on the surface morphology, crystal quality, strain, C incorporation, and growth kinetics of the Ge1-yCy layers. This work describes an exciting new possibility for the ultimate goal of incorporating high-mobility semiconductor materials in CMOS technology.
Silicon-based vertical MOSFETs
(2004) Jayanarayanan, Sankaran; Banerjee, Sanjay
For over three decades, the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has successfully undergone scaling to improve performance, and is presently at the sub-100 nm technology node. This has been possible due to several advances in the field, such as the introduction of copper interconnects, low-K dielectrics, silicided contacts, source-drain extensions, etc. Future scaling will require new materials such as strained silicon or silicon-germanium for channel mobility and drive current enhancement, high-K gate dielectrics to reduce the gate leakage current, and novel devices such as vertical MOSFETs or Fin-FETs to suppress short-channel effects. In this work, we have fabricated sub-100 nm silicon-based vertical MOSFETs, such as 70 nm strained and unstrained silicon-germanium vertical MOSFETs, 90 nm vertical MOSFETs with hafnium-oxide gate dielectric deposited by chemical vapor deposition (CVD), and a novel 50 nm Dielectric Pocket Vertical MOSFET (DPV- MOSFET) that shows excellent suppression of short channel effects. All samples were grown with the help of Ultra-high Vacuum Chemical Vapor Deposition (UHVCVD). We have demonstrated improved hole mobility and drive current in the SiGe PMOSFETs with a uniform Ge profile. However, the SiGe devices also had a higher leakage current and lower breakdown voltage due to the smaller bandgap of SiGe as compared to Si. The unstrained SiGe vertical MOSFETs were grown on a relaxed SiGe virtual substrate, and did not show a mobility enhancement, indicating that the improvement in mobility in strained SiGe is due to strain in the crystal lattice and not just Ge content. We observed conformal dielectric deposition and reduced gate leakage currents in the vertical MOSFETs with hafnium-oxide deposited by Rapid Thermal Chemical Vapor Deposition. The SiGe devices with CVD-HfO2 gate dielectric showed improved drive currents. We also fabricated a novel device called the DPV-MOSFET. Introduction of a dielectric pocket at the source-channel junction results in a device with a shallower equivalent source junction depth and hence reduced short-channel effects such as VTrolloff and drain induced barrier lowering (DIBL). Simulation results indicate that the device also a higher ION/IOFF ratio.
A study of HfO₂-based MOSCAPs and MOSFETs on III-V substrates with a thin germanium interfacial passivation layer
(2008-08) Kim, Hyoung-sub, 1966-; Lee, Jack Chung-Yeung
Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations.