# Browsing by Subject "Logic synthesis"

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Item Design automation for optical computing : Boolean logic and neural networks(2020-06-25) Zhao, Zheng, Ph. D.; Pan, David Z.; Chen, Ray T.; Sun, Nan; Ren, Haoxing; Touba, Nur AShow more As a promising alternative to traditional CMOS circuits, optics has demonstrated the ability to realize ultra-high speed and low-power information processing and communications. For optical computing tasks including Boolean logic and neural networks, however, there still exist challenges such as optical power efficiency, bulkiness and noise-robustness. To address the aforementioned issues, this dissertation proposes a set of algorithms, methodology, and architectures for optical computing tasks, which include: a synthesis flow that significantly reduces the optical power loss; a set of synthesis algorithms that exploits wavelength-division multiplexing (WDM) for area-efficient optical logic construction; a hardware-software codesign methodology that generates more area-efficient and robust ONNs; and an on-chip, integratable photonic Elman RNN architecture that empowers photonic RNNs the capability of training and tuning the state transformation for the first time. For the first work, we study the long-neglected optical power depletion problem in previous optical boolean logic synthesis, and propose graph transform techniques along with the exploitation of better optical devices to address this problem. The experiments where various sources of optical power depletion are considered, show the efficacy of our method of generating optical power efficient optical circuits, which also helps to build a much more robust and scalable integrated photonic system. In the second work, we exploit a special property of light in optical logic synthesis to reduce the number of optical components. The great potential of adopting WDM for efficient optical logic construction, is pinpointed and a systematic synthesis flow is designed considering the practical capacity constraint. Mathematically, we demonstrate the affinity of the capacity-constrained synthesis problem to the hypergraph partitioning and the min-cost max-flow problem. The experiments show the efficiency and efficacy of our method to generate smaller optical implementations for higher optical packaging density. In the third and fourth work, we focus on optical analog computing, more specifically, optical neuromorphic computing. We study the hardware-software co-design of a slimmed architecture for optical neural networks. The proposed methodology directly considers the structures and constraints of the optical hardware implementation during the software training process. The new design greatly reduces the number of optical components in the previous architecture, leading to a smaller optical hardware implementation. The reduction of the cascaded optical components also brings about better robustness against device and environment-related noise. In the fourth work, we propose the first photonic RNN architecture realizing the widely-used Elman RNN model to facilitate the applications with sequential information. To compensate for the delay variation due to manufacturing imperfections and/or the environmental change, we further introduce a hardware remediation mechanism along with a software training flow to selectively apply remediation to the most sensitive parts. The simulation showed we could effectively reduce the performance degradation by using the proposed flow. The effectiveness of proposed algorithms and techniques is demonstrated in this dissertation. These approaches can achieve the improvements regarding specific metrics and eventually advance the design of more compact, energy-efficient, and robust optical computing circuits.Show more Item Modeling and synthesis of approximate digital circuits(2014-12) Miao, Jin; Orshansky, Michael; Gerstlauer, Andreas, 1970-Show more Energy minimization has become an ever more important concern in the design of very large scale integrated circuits (VLSI). In recent years, approximate computing, which is based on the idea of trading off computational accuracy for improved energy efficiency, has attracted significant attention. Applications that are both compute-intensive and error-tolerant are most suitable to adopt approximation strategies. This includes digital signal processing, data mining, machine learning or search algorithms. Such approximations can be achieved at several design levels, ranging from software, algorithm and architecture, down to logic or transistor levels. This dissertation investigates two research threads for the derivation of approximate digital circuits at the logic level: 1) modeling and synthesis of fundamental arithmetic building blocks; 2) automated techniques for synthesizing arbitrary approximate logic circuits under general error specifications. The first thread investigates elementary arithmetic blocks, such as adders and multipliers, which are at the core of all data processing and often consume most of the energy in a circuit. An optimal strategy is developed to reduce energy consumption in timing-starved adders under voltage over-scaling. This allows a formal demonstration that, under quadratic error measures prevalent in signal processing applications, an adder design strategy that separates the most significant bits (MSBs) from the least significant bits (LSBs) is optimal. An optimal conditional bounding (CB) logic is further proposed for the LSBs, which selectively compensates for the occurrence of errors in the MSB part. There is a rich design space of optimal adders defined by different CB solutions. The other thread considers the problem of approximate logic synthesis (ALS) in two-level form. ALS is concerned with formally synthesizing a minimum-cost approximate Boolean function, whose behavior deviates from a specified exact Boolean function in a well-constrained manner. It is established that the ALS problem un-constrained by the frequency of errors is isomorphic to a Boolean relation (BR) minimization problem, and hence can be efficiently solved by existing BR minimizers. An efficient heuristic is further developed which iteratively refines the magnitude-constrained solution to arrive at a two-level representation also satisfying error frequency constraints. To extend the two-level solution into an approach for multi-level approximate logic synthesis (MALS), Boolean network simplifications allowed by external don't cares (EXDCs) are used. The key contribution is in finding non-trivial EXDCs that can maximally approach the external BR and, when applied to the Boolean network, solve the MALS problem constrained by magnitude only. The algorithm then ensures compliance to error frequency constraints by recovering the correct outputs on the sought number of error-producing inputs while aiming to minimize the network cost increase. Experiments have demonstrated the effectiveness of the proposed techniques in deriving approximate circuits. The approximate adders can save up to 60% energy compared to exact adders for a reasonable accuracy. When used in larger systems implementing image-processing algorithms, energy savings of 40% are possible. The logic synthesis approaches generally can produce approximate Boolean functions or networks with complexity reductions ranging from 30% to 50% under small error constraints.Show more